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SoC Engineer, Physical Design

Synopsys
November 2, 2026
Full-time
On-site
Ho Chi Minh City, Vietnam
Physical Design Jobs, Level - Senior

Job Title

SoC Engineer, Physical Design

Role Summary

Responsible for implementing SoC physical design flows and delivering production-ready designs using Synopsys EDA tools. Work within the SoC Engineering team to support customer projects, develop tool/IP solutions, and collaborate with business units and sales.

Focus areas include place-and-route, timing closure, extraction, physical verification, and mentoring junior engineers.

Experience Level

Senior - 8 to 12 years of relevant industry experience in place-and-route and physical design.

Responsibilities

Primary responsibilities include delivery, support, and technical leadership across SoC physical design projects.

  • Develop and implement SoC physical designs from RTL/Verilog through GDS using Synopsys tools.
  • Execute place-and-route flows and perform timing closure, extraction, and signoff checks.
  • Provide technical advisory and CAD support to customer design teams and internal stakeholders.
  • Collaborate with BU AE, Sales, and other Synopsys teams to broaden and deploy tool and IP solutions.
  • Innovate solutions to technical problems and drive process improvements with minimal supervision.
  • Mentor and provide technical guidance to junior team members.
  • Meet task-level goals and project schedules; document outcomes and share best practices.

Requirements

Must-have technical skills and experience for immediate contribution. Education requirements are listed separately below.

  • 8–12 years hands-on experience in place-and-route domains using Fusion Compiler/ICC2.
  • Strong debugging skills and practical understanding of P&R flows, extraction, timing, IREM, and physical verification fundamentals.
  • Proficiency in scripting (TCL, PERL) for flow automation and tool integration.
  • Experience communicating technical concepts in English and working with cross-functional teams.
  • Proven ability to guide and mentor junior engineers and manage task-level delivery.
  • Familiarity with signoff tools (PrimeTime, RedHawk, StarRC, ICV) is advantageous.

Education Requirements

BS, MS, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or a closely related technical field.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-10-28