SOC Design Verification Engineer, Staff – Pre-Si/Post-Si Verification

Job Title

SOC Design Verification Engineer, Staff – Pre-Si/Post-Si Verification

Role Summary

Work on pre-silicon and post-silicon verification of SoCs used in mobile, AI, high-performance computing and cloud products. The role covers simulation, emulation/acceleration, firmware/ATE correlation and silicon bring-up to achieve verification signoff.

Responsibilities scale by level: Engineer-level focuses on executing verification tasks and debug; Senior/Staff-level owns feature verification, leads complex debug across flows and mentors junior engineers.

Experience Level

Senior (Staff). Typical guidance: Engineer-level ~2+ years; Senior/Staff-level ~4+ years of relevant ASIC/SoC verification, validation, or silicon bring-up experience.

Responsibilities

Primary pre-silicon and post-silicon verification and validation activities.

• Develop and execute verification plans for SoC, subsystems and IP across pre- and post-silicon phases.
• Build, enhance and maintain SystemVerilog/UVM, C/C++, processor-based, emulation and acceleration verification environments.
• Create directed, constrained-random, stress, performance, power and system-level test scenarios.
• Develop assertions, functional coverage models, checkers, scoreboards and signoff metrics.
• Debug RTL, testbench, emulation, firmware, ATE/vector and silicon bring-up issues using logs, waveforms and hardware debug data.
• Support post-silicon validation, silicon characterization, ATE pattern debug, failure triage and correlation with pre-silicon results.
• Drive coverage closure, regression health, bug tracking and verification signoff using multiple coverage metrics.
• Participate in architecture, micro-architecture, design and validation reviews to capture verification requirements early.
• For Senior: own feature/subsystem verification from plan to closure, lead cross-team debug, mentor engineers and drive methodology/automation improvements.

Requirements

Must-have technical skills and demonstrated experience required for the role; preferred items listed separately.

• Engineer: ~2+ years relevant design verification, validation or SoC debug experience; Senior: ~4+ years with demonstrated ownership of complex verification or bring-up deliverables.
• Strong experience with SystemVerilog, UVM and assertion-based verification; C/C++ for tests and firmware.
• Experience with coverage-driven verification, regression frameworks and debug flows.
• Understanding of post-silicon validation concepts including bring-up, ATE/vector debug and silicon failure triage.
• Solid understanding of computer architecture, digital design fundamentals and SoC integration concepts.
• Strong debugging, problem-solving, communication and collaboration skills.
• Preferred: emulation/acceleration platforms (Veloce, Palladium, ZeBu), memory/PCIe/CXL/high-speed interface verification, AI/ML accelerator, power-aware verification, formal methods and firmware-driven validation.
• Preferred: scripting and automation skills (Python, Perl, shell) and experience with silicon debug tools (e.g., Trace32).

Education Requirements

Posting references Bachelor's, Master's or PhD in Science or Engineering (examples: Electrical Engineering, Computer Engineering, Computer Science or related technical fields). It lists degree-based alternatives (Bachelor's + experience, Master's + less experience, or PhD). Equivalent practical experience is implied by the experience-based alternatives.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.