SOC Design Verification Engineer – Pre-Si/Post-Si Verification

Job Title

SOC Design Verification Engineer – Pre‑Si/Post‑Si Verification

Role Summary

Join the Pre‑Silicon and Post‑Silicon SoC verification team to verify next‑generation SoCs across pre‑silicon simulation, emulation, acceleration, and post‑silicon bring‑up and validation. Work includes subsystem and full‑chip verification for mobile, AI, high‑performance computing, and cloud products.

Experience Level

Mid‑level and Senior roles. Engineer: typically 2+ years of relevant design verification, validation, or SoC debug experience. Senior Engineer: typically 4+ years with demonstrated ownership of complex verification, validation, or silicon bring‑up deliverables.

Responsibilities

Primary responsibilities across pre‑silicon and post‑silicon verification (scope varies by level):

• Develop and execute verification plans for SoC, subsystem, and IP features across pre‑silicon and post‑silicon phases.
• Build, enhance, and maintain SystemVerilog/UVM, C/C++, processor‑based, emulation, and acceleration verification environments.
• Create directed, constrained‑random, stress, performance, power, and system‑level tests; develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics.
• Debug RTL, testbench, emulation, firmware, ATE/vector, and silicon bring‑up issues using logs, waveforms, traces, and hardware debug data.
• Support post‑silicon validation, silicon characterization, ATE pattern debug, failure triage, and correlation between simulation, emulation, and silicon results.
• Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
• Participate in architecture, micro‑architecture, design, validation, and test‑plan reviews to ensure verification and bring‑up requirements are captured early.
• Senior level: own feature/subsystem verification from plan to closure, lead cross‑team debug, mentor engineers, and drive methodology and automation improvements.

Requirements

Must‑have technical skills and experience:

• Strong knowledge of SystemVerilog, UVM, C/C++, assertion‑based verification, and coverage‑driven verification.
• Experience with verification environments from architecture/specification through signoff, including regression and debug flows.
• Understanding of post‑silicon validation concepts: bring‑up, ATE/vector debug, hardware/software interaction, and failure triage.
• Solid understanding of computer architecture, digital design fundamentals, and SoC integration concepts.
• Demonstrated debugging skills using logs, waveforms, traces, and hardware debug data.
• Familiarity with emulation/acceleration platforms and correlation across simulation, emulation, and silicon.
• Proficiency in Python, Perl, or shell scripting for automation, regression, and data analysis.
• Excellent communication, collaboration, ownership, and problem‑solving abilities.

Nice‑to‑have:

• Experience with CPU, cache coherency protocols (ACE, CHI, CXL), DDR/LPDDR/HBM, PCIe, Ethernet, AI accelerators, security, RAS, performance, or power features.
• Experience with Veloce, Palladium, ZeBu, Portable Stimulus, formal verification, power‑aware verification, firmware‑driven validation, hardware/software co‑verification, or Trace32 debug tools.

Education Requirements

Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related science/engineering field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.