Physical Design Engineer
SyntiantJob Title
Physical Design Engineer
Role Summary
Join the ASIC R&D team to lead physical design implementation for next-generation Syntiant ASICs. The role owns RTL-to-GDSII flow and works cross-functionally with verification, package, and foundry partners to deliver optimized performance, power and area (PPA).
Experience Level
Mid-level — typically requires around 5+ years of industry experience in physical design and implementation.
Responsibilities
Deliver and optimize full-chip physical implementation, coordinate signoff activities, and support tape-out readiness.
- Drive RTL-to-GDSII physical implementation: synthesis, pad ring, floorplan, placement, CTS, routing, and optimization.
- Perform physical signoff and timing closure to meet PPA targets.
- Collaborate with physical verification team to resolve LVS/DRC/PERC and layout violations.
- Execute signoff ECO flows to fix timing, noise, IR-drop and EMIR issues.
- Coordinate with foundry on tape-out documentation, forms and checks.
- Contribute to package and RDL routing design and integration activities.
Requirements
Core technical skills and hands-on experience required for the role.
- Proven expertise in RTL-to-GDSII physical flow and industry-standard EDA tools for physical design and timing signoff.
- Strong knowledge of physically aware synthesis, floorplanning, place & route, metal fill, chip finishing, and clock tree synthesis.
- Experience with signal integrity checks, static/dynamic IR/EM analysis, and formal ESD verification.
- Experience building chip floorplans including partitions and power grid design.
- Experience in physical verification debugging for LVS/DRC/PERC at chip/block level using standard tools.
- Familiarity with UPF power intent flows and signoff ECO processes.
- Experience scripting with Python, Perl, or Tcl for automation and flow integration.
- Experience communicating with foundry on tape-out requirements and job view processes.
Nice-to-have:
- Scan insertion and ATPG pattern generation experience.
- Experience with power analysis flows.
Education Requirements
Advanced degree in electronics engineering (e.g., Master's or PhD) was requested in the source posting; the role is paired with 5+ years of physical design experience.
About the Company
Company: Syntiant
Headquarters: Irvine, California, United States
Syntiant develops ultra-low-power AI semiconductors and software for edge devices, including deep neural network processors and model architectures for speech, audio, sensor and vision applications. The company provides hardware-agnostic software and chips for consumer and industrial edge AI use cases.
