SOC Design Verification Engineer

Job Title

SOC Design Verification Engineer

Role Summary

Member of the Hard IP Division within Central Engineering Group responsible for defining and executing end-to-end verification strategy for multiple testchips from planning through functional signoff. The role partners with architecture, design, structural design, IP, and post-silicon teams to ensure predictable, high-quality delivery.

Primary focus on subsystem and SoC-level verification, driving reusable verification environments, coverage closure, and adoption of simulation, formal, and AI-assisted verification flows.

Experience Level

Mid-level — typically requires 5+ years of relevant design verification experience focused on subsystem and SoC verification.

Responsibilities

Own verification strategy and execution for critical blocks and testchips; ensure delivery of verification collateral and functional signoff.

• Define verification strategy, technical standards, and execution model for complex IP and testchips.
• Develop reusable environments, tools, testplans, complex testbenches, checkers, VIPs, and behavioral models.
• Collaborate across architecture, RTL design, structural design, methodology, and post-silicon teams from spec through bring-up.
• Drive coverage closure, functional signoffs, and gate-level simulation (GLS) signoff for owned blocks.
• Integrate simulation and formal verification into unified bug-hunting and coverage strategies; evaluate and adopt emerging methods including AI-driven flows.
• Mentor and develop junior verification engineers; document and enforce verification best practices.

Requirements

Must-have technical skills and experience required to perform the role.

• Extensive experience in subsystem and SoC-level verification, including verification of debug, trace, clock and power management functions.
• Strong background in simulation and formal verification methodologies: UVM, SVA, ABV, and co-simulation.
• Proficiency in SystemVerilog/UVM, HDL/verification languages, and industry-standard EDA tools.
• Advanced hands-on coding in C/C++ and Python; experience with build systems and automation.
• Practical experience with low-power verification techniques and VIPs.
• Working familiarity with RTL and physical design constraints and tool flows sufficient to read and review RTL and correlate with physical implementation.
• Strong communication, organizational skills, and a track record of delivering silicon on schedule.

Education Requirements

BS or MS in Electrical Engineering, Computer Science, or a related technical field. The posting specifies 5+ years of relevant design verification experience as the practical experience expectation.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.