SoC Design & Synthesis Engineer
QualcommJob Title
SoC Design & Synthesis Engineer
Role Summary
Develop and execute RTL-to-gate synthesis for large SoC designs, producing PD-ready gate-level netlists that meet timing, power and DFT requirements. The role owns synthesis inputs and multi-stage flows, supports functional ECOs, and drives PPA improvements through analysis and constraint/design recommendations.
The position works closely with Design, DFT, and Physical Design teams to resolve issues early and deliver manufacturable SoC implementations for Snapdragon-class products.
Experience Level
Mid-level. Minimum commonly expected experience is 2+ years in ASIC design/verification/validation or related work; preferred candidates have ~3+ years and experience with synthesis and architecture/design tools.
Responsibilities
Primary duties include preparing and executing synthesis flows, ensuring netlist quality, and supporting handoff to Physical Design.
- Execute RTL-to-gate synthesis for IP blocks and full SoC flows; manage multi-stage synthesis pipelines.
- Own synthesis inputs, constraints and scripts; produce PD-ready gate-level netlists and reports.
- Define and validate timing constraints (SDC) across functional and test modes.
- Perform gate-level netlist quality checks and handoff verification for timing, power and DFT readiness.
- Analyze and optimize PPA (Power, Performance, Area) trade-offs; recommend design or constraint changes.
- Support and implement functional ECOs; validate post-change correctness and functionality.
- Collaborate with Design, DFT, and Physical Design teams to triage and resolve issues early in the flow.
- Document synthesis flows, maintain reproducible scripts and technical reports.
Requirements
Required technical skills and experience for performing the role effectively.
- Must have: Practical experience with RTL-to-gate synthesis for large SoC designs, gate-level netlist quality checks, and PD-ready handoffs.
- Must have: Proficiency defining and validating timing constraints (SDC) across modes and performing timing/power analysis.
- Must have: Experience supporting functional ECOs and validating post-change correctness.
- Must have: Ability to analyze and optimize PPA trade-offs and recommend constraint or design changes.
- Must have: Strong debugging, analytical thinking, and ability to execute under tight schedules; scripting skills for flow automation.
- Nice to have: Experience with architecture and design tools, verification methods, and specific EDA synthesis tools or full RTL-to-GDS flows.
Education Requirements
Minimum: Bachelor's degree in Science, Engineering, or related field plus 2+ years of ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or related field plus 1+ year of related experience; OR PhD in Science or Engineering. Preferred: Master's in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. (Related technical fields are acceptable per the posted minimum/ preferred qualifications.)
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
