SoC Design Implementation Engineer (Up to Principal Level)

Job Title

SoC Design Implementation Engineer (Up to Principal Level)

Role Summary

Contribute to front-end implementation and synthesis of complex SoC, subsystem and IP designs, producing clean netlists and implementation collateral for downstream physical design, DFT, verification, emulation, and signoff teams.

Work cross-functionally with RTL designers, architecture, physical design, DFT, CAD/methodology, power-management, and program teams to resolve timing, power, synthesis, and flow issues.

Experience Level

Open at levels from Engineer through Principal. Typical guidance: entry Engineer roles ~3+ years; Senior/Staff/Principal roles require progressively more experience (see Education Requirements for specific year ranges associated with degrees).

Responsibilities

Deliver implementation readiness and resolve front-end issues from block to SoC level.

• Support RTL-to-netlist implementation: synthesis runs, netlist generation, reports, and handoff collateral.
• Develop, review, and maintain timing constraints and ensure multi-mode/multi-corner readiness.
• Analyze timing reports, identify critical paths and QoR issues; debug unconstrained paths and constraint propagation problems.
• Tune synthesis strategies and resolve synthesis warnings, inferred structures, unintended latches, multiple drivers, and library mismatches.
• Integrate and validate UPF-based power intent; debug supply-domain, isolation, and retention issues (where applicable).
• Coordinate design releases, configuration, and readiness with RTL, DV, PD, DFT, CAD, and architecture teams.
• Drive implementation quality closure across lint, CDC/RDC, connectivity, formal, and signoff checks.
• Document assumptions, methodology decisions, and handoff requirements; mentor junior engineers.

Requirements

Must-have technical skills and practical experience; degree details are listed below under Education Requirements.

• Must-have: Practical experience with Verilog/SystemVerilog and RTL coding practices, RTL hierarchy and clock/reset structures.
• Must-have: Hands-on experience with RTL-to-gate synthesis flows, netlist review, and QoR analysis for timing/area/power.
• Must-have: Experience developing and validating timing constraints, static timing analysis, and timing debug (clocks, generated clocks, I/O delays, exceptions).
• Must-have: Ability to investigate and resolve synthesis/implementation failures across RTL, constraints, UPF, libraries, and tool configuration.
• Must-have: Strong cross-functional collaboration, communication, and problem-solving skills.

• Nice-to-have: Experience with UPF/power intent, low-power implementation, and power-aware simulation.
• Nice-to-have: Familiarity with synthesis/STA/equivalence/lint/CDC tools and ASIC implementation flows (DFT, PD handoff, emulation, gate-level simulation).
• Nice-to-have: Scripting and automation skills (Tcl, Python, Perl, Shell) for flow automation and report analysis.
• Nice-to-have: Experience with standard on-chip interfaces (AXI, AHB, APB) and working in large, globally distributed semiconductor teams.

Education Requirements

The posting specifies degree-based and experience-based minimums. Findings across the posting include: a Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is listed as required in some sections; a Masters degree is preferred. Alternative qualification statements in the posting list the following equivalencies: Bachelors degree + 8+ years of relevant hardware engineering experience, OR Masters degree + 7+ years, OR PhD + 6+ years. The posting also references earlier guidance of ~3+ years of relevant experience for engineer-level roles. Equivalent practical experience is implied as an alternative in some sections.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.