SoC Compute/Memory Subsystem Architect

Job Title

Senior SoC Compute & Memory Architect

Role Summary

Join the Networking Architecture Group responsible for architecting compute and high-performance memory subsystems for IPU/DPU platforms. The role leads end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and system memory to optimize performance, scalability, power, and programmability for hyperscale and cloud workloads.

Experience Level

Senior — requires 10+ years of relevant industry experience in SoC/CPU/memory subsystem architecture.

Responsibilities

Accountable for system-level compute and memory architecture across multiple product generations and for aligning cross-functional teams to deliver balanced SoC performance.

• Define and evolve multi-level cache hierarchies and coherency models for compute cores, accelerators, and IO subsystems.
• Architect memory subsystems (DDR/LPDDR/HBM), memory controllers, scheduling policies, and bandwidth scaling strategies.
• Design SMMU/IOMMU and virtualization memory models to support multi-tenant IPU workloads with isolation and security.
• Integrate compute, network (packet-processing), storage, and accelerator subsystems to optimize data movement and minimize latency and copies.
• Define power-efficiency and DVFS strategies, memory bandwidth throttling/prioritization, and per-subsystem scaling mechanisms.
• Lead long-term architecture roadmaps: core scaling, memory bandwidth/capacity, cache topology, and cross-generation compatibility.
• Drive cross-functional alignment with networking, fabric/interconnect, firmware, OS/drivers, validation, and performance teams.

Requirements

Required technical experience and skills; preferred items noted separately.

• 10+ years of experience in SoC, CPU, and memory subsystem architecture, including cache hierarchies and coherency.
• Proven experience with memory subsystems (DDR/HBM), controllers, QoS, and system-level performance/PPA tradeoff analysis.
• Experience with coherent and non-coherent interconnect architectures and system integration across compute, IO, and accelerators.
• Demonstrated ability to define architecture from concept through silicon delivery and to produce system-level architecture tradeoffs.
• Strong systems thinking, cross-team leadership, and decision-making under ambiguity.
• Nice-to-have: ARM and x86 compute/memory experience, IPU/SmartNIC or accelerator-centric SoC exposure, familiarity with PCIe and CXL memory semantics, multi-generation architectural ownership and mentoring.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, or another STEM field. Preferred: Post-graduate degree in Electrical Engineering, Computer Engineering, or related STEM discipline.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.