SOC Clocks RTL Design Engineer

Job Title

SOC Clocks RTL Design Engineer

Role Summary

As an RTL Design Engineer on the NVIDIA System‑On‑Chip (SOC) team, you will own SOC clock generation, distribution, and control logic for next‑generation networking chips. You will translate micro‑architecture specifications into synthesizable Verilog/SystemVerilog RTL and drive the design through verification and physical implementation.

Experience Level

Mid-level — the role requests 3+ years of relevant RTL/logic design experience.

Responsibilities

Key responsibilities include:

• Design synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, dividers, glitchless switching, clock gating, and reset synchronization.
• Define and implement SOC clock and reset architecture from chip-wide requirements.
• Develop and maintain clock domain crossing infrastructure and drive CDC closure.
• Partner with micro-architecture, DV, backend (physical design), CAD, firmware/software, and DFT teams to align design intent and implementation.
• Collaborate with physical design on clock tree constraints, partitioning, floorplanning, synthesis QoR, congestion and timing convergence.
• Drive design quality: lint, CDC/RDC, formal checks, synthesis and connectivity checks; automate integration and quality flows.
• Support emulation, firmware, and post-silicon bring-up and downstream customers of the design.

Requirements

Must-have qualifications and skills:

• 3+ years of RTL/logic design experience translating micro‑architecture to synthesizable RTL and taking designs to silicon.
• Hands-on RTL skills in Verilog/SystemVerilog and practical understanding of synthesis and timing impact.
• Strong knowledge of clocking and reset concepts: clock gating, muxing/dividers, glitchless switching, reset synchronization, and CDC.
• Familiarity with design quality tooling: lint, CDC/RDC, formal, and synthesis tools.
• Proven collaboration and communication skills across micro‑architecture, DV, and backend teams.

Nice-to-have:

• Prior ownership of SOC-level clocking or reset architecture on a taped-out chip.
• Experience with PLL/clock generator integration and clock tree constraint development.
• Track record of clean deliveries to physical design, DV, emulation, and firmware teams.

Education Requirements

B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering (as stated in the source).

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.