SoC Clocking Specialist (Physical Design)

Job Title

SoC Clocking Specialist (Physical Design)

Role Summary

Lead clock architecture and physical implementation for next-generation edge AI SoCs. Work across Architecture, RTL, Physical Design and Timing teams to design, implement, and sign-off robust, low-power clock distribution on advanced process nodes.

Experience Level

Senior - 8+ years of semiconductor physical design experience with a strong focus on clocking architecture and implementation.

Responsibilities

Primary responsibilities span clock tree architecture, implementation, verification, and cross-functional alignment to achieve timing closure and power targets.

• Collaborate with SoC Architecture and RTL teams to define clocking schemes, clock gating strategies, and synchronous/asynchronous boundaries.
• Own end-to-end Clock Tree Synthesis (CTS) strategy and coordinate with Physical Design and STA teams to minimize skew and insertion delay.
• Run detailed SPICE simulations on critical clock paths to analyze jitter, duty-cycle distortion, slew degradation, and local variation.
• Architect clock distribution networks (trees, meshes, hybrid topologies) balancing high-frequency performance and dynamic power.
• Integrate and validate high-speed clocking IPs (PLLs, DLLs, oscillators) into the top-level clock network.
• Develop and refine CTS and SPICE analysis methodologies to improve silicon predictability from RTL to GDSII.
• Support timing closure, sign-off checks, and cross-team issue resolution during bring-up and tapeout phases.

Requirements

Must-have technical skills and practical experience required for the role; preferred items listed separately.

• Must-have: Deep practical experience with clock tree design and CTS methodologies on advanced process nodes.
• Must-have: Hands-on experience running and interpreting SPICE simulations for clock networks.
• Must-have: Strong knowledge of STA constraints, jitter budgeting, cross-talk, and variation modeling.
• Must-have: Proficiency with industry EDA physical design and timing tools (examples: Synopsys ICC2/PrimeTime, Cadence Innovus/Tempus).
• Must-have: Scripting skills (Python, Tcl, or Perl) to automate flows and analyze large timing datasets.
• Must-have: Excellent communication and cross-functional collaboration skills to align Frontend, DV, PD, and sign-off teams.
• Preferred: Experience with HSPICE, CustomSim or other circuit simulators; prior work on ultra-low-power or high-frequency edge-AI designs.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI Design, or a closely related field. The role expects ~8+ years of experience in semiconductor physical design with a focus on clocking architecture and implementation.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.