SOC Clock Distribution Engineer
Design and implement SoC-level clock distribution solutions for complex chips, focusing on physical integration, timing, and power-constrained layouts. Work within the SOC physical design organization and coordinate with unit owners, CAD, package design, software, DFT and verification teams to ensure clocking meets functional and quality requirements.
This role involves hands-on clocking design, root-cause debug of timing/layout issues, and enabling chip delivery across RTL, physical design and downstream teams.
Mid-level β requires at least 3 years of confirmed chip design experience.
The main responsibilities involve SoC clock architecture, implementation, and cross-functional integration.
Concise list of required skills and attributes followed by distinguishing qualifications.
B.Sc. in Electrical Engineering or Computer Engineering specified in the posting.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
