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SOC Clock Distribution Engineer

NVIDIA
June 05, 2026
Full-time
On-site
Tel Aviv-Yafo, Israel
Physical Design Jobs, Level - Mid-Career

Job Title

SOC Clock Distribution Engineer

Role Summary

Design and implement SoC-level clock distribution solutions for complex chips, focusing on physical integration, timing, and power-constrained layouts. Work within the SOC physical design organization and coordinate with unit owners, CAD, package design, software, DFT and verification teams to ensure clocking meets functional and quality requirements.

This role involves hands-on clocking design, root-cause debug of timing/layout issues, and enabling chip delivery across RTL, physical design and downstream teams.

Experience Level

Mid-level β€” requires at least 3 years of confirmed chip design experience.

Responsibilities

The main responsibilities involve SoC clock architecture, implementation, and cross-functional integration.

  • Define and implement SoC-level clock requirements and distribution schemes.
  • Partition clock domains and manage clock domain crossing (CDC) issues.
  • Perform trial synthesis, timing closure checks, and design quality validations.
  • Debug functional and structural clocking issues and drive fixes to closure.
  • Ensure physical design readiness and resolve layout and timing constraints.
  • Collaborate with Physical Design, CAD, Package Design, RTL owners, Software and DFT teams.

Requirements

Concise list of required skills and attributes followed by distinguishing qualifications.

  • Must-have: 3+ years of hands-on chip design experience, with demonstrated physical design skills in clock distribution for multi-power and timing/layout constrained products.
  • Must-have: Practical experience with clock partitioning, CDC, trial synthesis, timing closure and design quality checks.
  • Must-have: Proficiency in scripting (Perl, Python, Bash, or Tcl) for automation and analysis.
  • Must-have: Strong collaboration and communication skills; effective teammate in cross-functional engineering teams.
  • Nice-to-have: Experience delivering corrections back to RTL and coordinating fixes through physical implementation and downstream verification.
  • Nice-to-have: Demonstrated focus on delivery quality and production-ready chip releases.

Education Requirements

B.Sc. in Electrical Engineering or Computer Engineering specified in the posting.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-06-05