SoC Architect

Job Title

SoC Architect

Role Summary

Own the detailed SoC-level architecture for dies used in Volantis wafer-scale systems (A-0 and A-1). Work with architecture and ASIC design teams to produce implementable specifications and drive implementation through tapeout and silicon bring-up.

Experience Level

Senior-level (Architect). Typically suited to candidates with extensive SoC architecture ownership; experience on multiple tapeouts or equivalent senior engineering ownership is expected.

Responsibilities

Primary responsibilities focus on specifying and delivering SoC designs that meet system, performance, and integration targets.

• Define detailed SoC-level architecture and microarchitecture for assigned dies.
• Produce clear, implementable specifications and design handoff materials for RTL, physical design, and verification teams.
• Coordinate across architecture, ASIC design, package, memory-subsystem, and IO teams to ensure correct integration and interfaces.
• Drive design decisions to meet PPA, timing, and manufacturability targets for large-die/wafer-scale systems.
• Support silicon bring-up, debug, and iteration activities to achieve production-quality A0/A1 silicon.

Requirements

Must-have technical experience and skills; separate nice-to-have capabilities are listed below.

• Must have: Ownership of specifications and led implementation for at least one SoC/die.
• Must have: Deep understanding of architecture, microarchitecture, and physical design flows and how to coordinate implementation across groups.
• Must have: Knowledge of SoC interactions with packages, memory subsystems, and IO, and experience working with teams responsible for those blocks.
• Nice to have: Experience with multi-die, chiplet, or MCM designs.
• Nice to have: Experience with reticle-max/large-die SoC architecture and levers for improving PPA.
• Nice to have: Track record of high-speed A0 silicon delivery.

Education Requirements

Not specified.

About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.