SMTS IO/Clock Design Engineer

Job Title

SMTS IO/Clock Design Engineer

Role Summary

Senior analog/mixed-signal engineer on the IP Design team responsible for architecting, designing, optimizing, verifying and supporting high-speed IO and clocking circuits for Micron DRAM products. The role focuses on equalization, bandwidth extension, timing and jitter analysis, and delivering engineering solutions that meet silicon and system timing targets.

Experience Level

Senior; this role expects an experienced engineer with substantial industry experience in high-speed IO and clocking circuit design (senior-level technical contributor and mentor).

Responsibilities

Key responsibilities include:

• Define, design, optimize and verify high-speed IO and clocking circuits for new DRAM products.
• Apply high-speed circuit design techniques and evaluate timing, jitter sensitivity, and duty-cycle distortion at circuit and full-chip level.
• Develop modeling, analysis and simulation methodologies to predict circuit performance and its impact on product and system specifications.
• Analyze IO impairments and clock jitter, assess impacts on DRAM system timing, and implement mitigation strategies (equalization, bandwidth extension, etc.).
• Support silicon validation and correlation by working with Product Engineering and Signal Integrity teams to compare silicon results with simulations.
• Collaborate with process integration and transistor modeling teams on next-node process and device interactions.
• Provide technical support and mentoring to less-experienced engineers and oversee layout practices to minimize parasitic impacts.

Requirements

Must-have technical skills and expectations:

• Extensive industry experience designing high-speed IO interfaces, timing and clocking circuits with demonstrated silicon successes.
• Strong analog/mixed-signal circuit design skills focused on equalization, bandwidth extension, and jitter/timing analysis.
• Ability to supervise and review layout for high-speed circuits and understand layout practices to minimize parasitics.
• Proven communication skills to explain complex technical concepts in writing and verbally.
• Ability to work concurrently across multiple product teams and support silicon validation efforts.
• Demonstrated mentoring and coaching experience for early-career engineers.

Nice-to-have:

• Prior DRAM circuit design experience.
• Experience with channel modeling, transceiver noise and timing budget analysis, equalization techniques, and signal integrity.
• Understanding of device physics and basic CMOS processing.
• Experience applying AI/ML and scripting (Perl, Python) to design or analysis workflows.

Education Requirements

Minimums stated in the source: MSEE plus 10 years of industry experience, or BSEE plus 12 years of industry experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.