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Simulator & Debug Tools Lead

Normal Computing
October 23, 2026
Full-time
On-site
Mountain View, California, United States
EDA Jobs, Level - Senior

Job Title

Simulator & Debug Tools Lead

Role Summary

Lead design and delivery of the hardware simulator and the debugging/profiling tools that integrate with the compiler and runtime teams. Partner with design verification and bring-up to ensure simulator fidelity matches hardware behavior.

This is a hands-on technical leadership role that balances simulator accuracy, execution speed, and developer tooling investment.

Experience Level

Senior - technical lead role. Expect substantial experience building or directing simulator and tooling development for hardware or novel compute architectures.

Responsibilities

Own the simulator, its tooling, and its correlation with hardware. Key responsibilities include:

  • Define and maintain simulator architecture and roadmap covering accuracy, performance, and new hardware features.
  • Ensure behavioral correctness of simulator state and memory semantics so compiler/runtime engineers can rely on results.
  • Design and implement debuggers, tracers, and profilers used by engineers to find and fix bugs quickly.
  • Correlate simulator outputs with RTL, FPGA prototypes, and silicon; drive closure on disagreements.
  • Develop workload benchmarks and LLM inference traces to validate simulator fidelity against real workloads.
  • Prioritize investments between fidelity, speed, and tooling and communicate tradeoffs to stakeholders.

Requirements

Must-have:

  • Proven experience building or leading development of hardware simulators (cycle-accurate or functional) for ASICs or novel compute architectures.
  • Strong systems and compiler context sufficient to simulate the software stack that runs on the hardware.
  • Fluency in C++ or Rust for simulator performance and familiarity with Python for tooling.
  • Experience building debuggers, tracers, or profilers that engineering teams adopt.
  • Comfort working with evolving hardware and adapting the simulator accordingly.

Nice-to-have:

  • Experience with in-memory compute or other non-von-Neumann architectures.
  • Experience using simulators to inform architectural or compiler decisions rather than only post-hoc validation.
  • Experience with open-source simulation, tracing, or hardware-tooling communities.
  • Background spanning both pre-silicon simulation and post-silicon bring-up.

Education Requirements

Not specified.


About the Company

Company: Normal Computing

Headquarters: New York, NY, USA

Normal Computing develops software and hardware solutions for the semiconductor and AI infrastructure industries, specializing in ASICs for image and video diffusion inference and AI accelerators. The company focuses on architecture and microarchitecture of compute blocks, PE array design, ISA co-design, and FPGA prototyping.

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Date Posted: 2026-10-22