Silicon Validation Engineer

Job Title

Silicon Validation Engineer

Role Summary

Work on silicon bring-up and validation for advanced SoCs used in high-performance ML systems. You will own chip bring-up, validate functionality and performance across lab, emulation, and system environments, and collaborate with architecture, design, DV, firmware, and software teams.

This role is based in Mountain View with an in-office cadence of Tuesdays–Thursdays.

Experience Level

Mid-level (Level - Mid-Career). The posting does not specify exact years of experience.

Responsibilities

Deliver post-silicon and chip-level validation from first power-on to production readiness and improve correlation between pre-silicon and silicon environments.

• Plan and execute validation for chip and SiP functionality, performance, reliability, and system behavior.
• Own silicon bring-up: boot, reset, initialization, power management, recovery, memory, interconnect, and package-level validation.
• Work across top-level DV, hardware emulation (e.g. Palladium), lab validation, and package-level testing to improve coverage and correlation.
• Debug complex failures using logs, registers, traces, waveforms, firmware output, and lab instrumentation.
• Analyze issues spanning RTL, firmware, software, board, package, and silicon boundaries and drive to root cause.
• Define observability and debug requirements and improve validation automation and failure triage.
• Collaborate cross-functionally with architecture, design, DV, emulation, firmware, software, and product teams.

Requirements

Must-have skills and domain experience for successful execution of the role.

• Hands-on silicon validation, post-silicon bring-up, or hardware emulation experience validating complex SoCs or accelerators.
• Strong understanding of digital hardware, SoC architecture, and hardware–firmware interactions.
• Proven ability to debug cross-functional failures and drive them to root cause using logs, traces, waveforms, and lab tools.
• Experience with real silicon and lab platforms and familiarity with embedded firmware, low-level drivers, and hardware access.
• Ability to read and understand C or C++ for debug; scripting experience in Python or similar.
• Strong ownership, clear communication, and effective cross-functional collaboration skills.
• Authorization to work in the United States and ability to work from the Mountain View office Tuesdays–Thursdays.

Nice-to-have:

• Experience with both pre-silicon and post-silicon validation and bringing up first silicon.
• Familiarity with Cadence Palladium, SystemVerilog/UVM, assertions, coverage, and waveform debug.
• Experience with HBM, DDR, PCIe, CXL, Ethernet, die-to-die interfaces, or advanced packaging.
• Experience with JTAG, oscilloscopes, logic analyzers, or protocol analyzers.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.