Silicon Power Architect, Reality Labs

Job Title

Silicon Power Architect, Reality Labs

Role Summary

Lead power architecture and estimation for custom SoC solutions used in AI-enabled wearables. Work with architects, PMIC and systems teams to define power states, sequences, and high-level power trees and to optimize implementations to meet use-case power goals.

Contribute across the design flow from high-level modeling through RTL and post-silicon correlation to enable low-power consumer wearable products.

Experience Level

Mid-level — typically requires 6+ years of experience with production silicon and at least one shipped product.

Responsibilities

Primary responsibilities include ownership of use-case power modeling, defining SoC-level power requirements, and coordinating across disciplines to drive designs to production.

• Model and own use-case power for custom silicon in collaboration with systems teams.
• Define and influence SOC IP power requirements: power states, high-level power tree, and power sequencing.
• Collaborate with SOC architects to optimize image compute, CPU/GPU, and other workloads for AR/VR products.
• Coordinate with PMIC and system teams on overall SOC power requirements and implementation trade-offs.
• Optimize power-architecture implementations to meet product use-case power targets.
• Drive cross-disciplinary initiatives from concept through prototype to high-volume product transition.
• Model data flows and perform cost/benefit analyses between general-purpose and custom compute approaches.
• Perform post-silicon model-to-hardware correlation and validation.

Requirements

Must-have technical experience and skills for the role; preferred skills are listed separately.

Must-have:

• 6+ years working with production silicon and at least one shipped product.
• Experience with power estimation, convergence tool flows, and power management methodologies.
• Experience partitioning solutions across hardware/software and multi-disciplinary system boundaries.
• Knowledge of technology-node scaling and projections.
• Experience producing custom IP block power estimates and applying low-power design principles at RTL, block, and system levels.
• Ability to evaluate architectural trade-offs among performance, power, and area.
• Proven use of scientific methods to diagnose and resolve cross-disciplinary system issues.

Nice-to-have:

• Experience leading or collaborating across hardware, software, and systems teams.
• Familiarity with high-level modeling tools (for example, Synopsys Platform Architect) or virtual prototyping.
• Experience driving technical workstreams and coordinating multi-team deliverables.
• Experience using AI agents to manage power tools and extract results.
• Experience scoping technical specifications for novel consumer silicon architectures and top-down system-level to HW power modeling.
• Programming experience in C, C++, or Python.
• Graduate-level degree (MSEE/PhD) is a plus.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience. A master’s degree (MSEE) or PhD is listed as preferred/optional.

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.