Silicon Physical Design Engineer

Job Title

Silicon Physical Design Engineer

Role Summary

Design and implement physical layouts for custom silicon targeting AR/VR wearable platforms, focusing on ML compute blocks. The role drives physical design strategy across the implementation flow (floorplanning, placement, CTS, routing, signoff) and collaborates with architecture, RTL, package, and process teams to meet power, performance, and area targets.

This is an engineering role on the Silicon Physical Design team working on consumer wearable SoCs and mixed-reality hardware.

Experience Level

Level - Senior. Guidance: 8+ years of physical design implementation experience.

Responsibilities

Deliver physical implementation and methodologies for complex silicon blocks and partner across disciplines to achieve signoff-quality chips.

• Lead implementation across floorplanning, placement, clock tree synthesis, routing, and signoff for complex custom silicon blocks.
• Collaborate with ML architects and designers to optimize PPA for ML datapath blocks.
• Define and drive physical design methodology, timing closure strategies, and power delivery network architecture.
• Develop and own implementation flows, scripts, and automation to improve QoR and turnaround time.
• Perform static timing analysis, power analysis, and physical verification (DRC, LVS, ERC) to achieve signoff closure.
• Partner with package and board engineers on bump maps, power delivery, and signal integrity for wearable form factors.
• Provide technical guidance on physical design best practices and work with foundry partners to resolve process-specific issues.

Requirements

Must-have technical skills and experience required for successful performance in this role.

• 8+ years of experience in physical design implementation for complex digital SoCs or custom silicon (floorplanning, placement, CTS, routing, signoff).
• Experience with advanced process nodes (3nm or below) and familiarity with foundry design rules, PDKs, and physical verification requirements.
• Proficiency with industry-standard EDA tools for physical implementation and signoff, including static timing analysis and power analysis.
• Experience defining or significantly contributing to physical design methodology, flows, or automation across multi-block or full-chip designs.
• Proven experience collaborating with RTL, architecture, and package engineering teams to co-optimize implementation decisions.

Nice-to-have:

• Scripting for physical design automation (Python, Tcl) to improve implementation efficiency and QoR.
• Experience with custom or semi-custom datapath design, standard cell characterization, or library development.
• Experience in low-power techniques for wearable/mobile SoCs (multi-voltage domains, power gating) and familiarity with 3D packaging or chiplet integration.

Education Requirements

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. (Equivalent practical experience is explicitly accepted in the posting.)

About the Company

Company: Meta Platforms

Headquarters: Menlo Park, California, United States

American technology company that develops social networking products (Facebook, Instagram, WhatsApp) and invests in virtual/augmented reality hardware and software through Reality Labs, focusing on connectivity, advertising, and immersive computing experiences.