Silicon Packaging Engineering Manager

Job Title

Silicon Packaging Engineering Manager

Role Summary

Lead a team that delivers advanced IC packaging solutions (EMIB, Foveros, chiplet architectures) for customer programs within Intel Foundry's Advanced Design and Customer Engineering organization. Act as the technical lead for package design execution, ensure first-pass success, and coordinate across architects, silicon/board teams, and analysis groups.

This is a leadership role focused on technical delivery, project execution, quality and cross-functional integration.

Experience Level

Senior-level manager. The role requires significant industry experience with at least 3 years in a leadership role; total years of experience expectations vary by education (see Education Requirements).

Responsibilities

You will manage people and projects, provide technical leadership for packaging design, and drive process and quality improvements.

• Manage and mentor a team of IC packaging engineers; set priorities and ensure project execution.
• Serve as primary package design technical lead and customer technical partner through end-to-end design flow.
• Oversee planning, scheduling, resource allocation, risk management, and progress tracking for package design projects.
• Coordinate cross-functional teams (package architects, silicon/board designers, electrical analysis, integration) to define and implement design specifications.
• Ensure design quality, manufacturability, yield awareness, and compliance with design rules and industry standards.
• Drive process improvements and incorporate new tools and methodologies to improve design efficiency and outcomes.
• Report project status and technical risks to senior management; lead design reviews and corrective actions.

Requirements

Must-have technical skills and experience required for initial consideration are listed below; preferred items are noted separately.

• Must-have: Experience in IC packaging, chiplet or SoC design, or heterogeneous integration with demonstrated package design execution.
• Must-have: At least 3 years in a leadership or management role overseeing engineering teams and delivering complex projects.
• Must-have: Experience with performance, manufacturability, and yield-aware design methodologies.
• Must-have: Familiarity with design flows and methodologies (physical design, electrical analysis, verification).
• Must-have: Hands-on experience with IC packaging EDA tools from Siemens and/or Cadence.
• Must-have: Strong cross-functional collaboration, project planning, and risk-management skills.
• Nice-to-have: Experience with IC packaging designs for HPC/AI-class products.

Education Requirements

Minimum qualifications specify one of the following: Bachelor's degree in Electrical Engineering or a STEM-related field plus 9+ years relevant experience; OR Master's degree in Electrical Engineering or a STEM-related field plus 6+ years relevant experience; OR PhD in Electrical Engineering or a STEM-related field plus 4+ years relevant experience. Additionally, relevant experience includes IC packaging, chiplet/SOC design or heterogeneous integration and leadership experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.