Silicon Packaging Design Architect

Job Title

Silicon Packaging Design Architect

Role Summary

Senior engineering role responsible for end-to-end package architecture and delivery for physical, electrical, thermal and cost targets. The role sits on the Silicon Packaging Architecture team and requires cross-functional collaboration with silicon, hardware, board, and EDA partners to move designs from concept to production.

This role requires on-site presence in Phoenix, AZ and work on advanced packaging and 3D IC solutions.

Experience Level

Level: Senior. Minimum experience guidance varies by degree: typically 6+ years (Bachelors), 4+ years (Masters), or 2+ years (PhD). Preferred candidates may have 10+ years of relevant experience.

Responsibilities

Primary responsibilities include defining package architecture, driving tradeoffs, and ensuring manufacturable, reliable package outputs.

• Translate product requirements into detailed package architecture and specifications.
• Drive technology tradeoff decisions across electrical, mechanical, thermal, and reliability domains.
• Lead end-to-end package development: design, procedures, validation, and continuous improvement.
• Troubleshoot packaging designs and resolve materials/process issues with cost-effective solutions.
• Implement silicon-to-board co-design strategies to optimize performance and cost.
• Collaborate with EDA partners to advance package design tools and workflows.
• Coordinate with cross-disciplinary teams to remove roadblocks and enable production transitions.

Requirements

Must-have technical skills, security and work-eligibility requirements.

• US Citizenship required and ability to obtain and maintain US Government TS/SCI clearance with Polygraph.
• 2+ years hands-on experience in semiconductor fabrication, chip assembly, or packaging.
• Experience with electromagnetic simulation tools (examples: Mentor, Cadence, SPICE, Ansys).
• Experience with Cadence Allegro (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity) and/or Mentor Xpedition (PCB Layout/XPD, Designer, HyperLynx).
• In-depth knowledge of assembly processes, test methodologies, and characterization techniques.
• Strong analytical, communication, and organizational skills; ability to manage multiple priorities.

Preferred / Nice-to-have:

• Active TS/SCI clearance with Polygraph.
• Extensive experience (e.g., 10+ years) in package, PCB or IC digital design and optimization.
• Proven troubleshooting and cost/quality optimization experience for packaging designs.
• Experience making technology trade-off decisions and working across multiple abstraction levels.

Education Requirements

Options listed in the posting: Bachelor's degree in electrical engineering, mechanical engineering, chemical engineering, materials science or a related STEM field (typically with 6+ years' experience); Master's in those fields (typically with 4+ years); or Ph.D. in those fields (typically with 2+ years). The posting also allows equivalent combinations of industry experience, internships, coursework or research in lieu of formal degrees.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.