Silicon Logic Design Engineer

Job Title

Silicon Logic Design Engineer

Role Summary

Senior RTL logic designer responsible for defining micro-architecture and delivering production-quality RTL for complex digital blocks used in memory subsystems and high-performance digital IP. The role works across architecture, verification, physical design, applications, and customer-facing teams and provides technical ownership from specification through integration.

Position is based in San Jose, CA (primary) or Hillsboro, OR, with a hybrid schedule (typically ~3 days onsite per week).

Experience Level

Senior-level. Typical experience expected: MSEE with ~8+ years of ASIC/FPGA logic design, or BSEE with ~10+ years.

Responsibilities

You will own design blocks from architecture through RTL implementation and integration, collaborate cross-functionally, and support customer and product engineering teams.

• Define micro-architecture and develop production-quality SystemVerilog/Verilog RTL for complex digital blocks.
• Design scheduling logic, command/transaction pipelines, ordering/coherency mechanisms, control logic, and high-performance interfaces.
• Evaluate PPA (performance, power, area) trade-offs and use quantitative analysis to guide decisions.
• Partner with verification to create strategies, identify corner cases, and improve functional coverage.
• Collaborate with physical design to resolve timing closure, power, utilization, and congestion issues.
• Investigate regression failures, perform root-cause analysis, and implement RTL fixes.
• Participate in design reviews, architecture discussions, and cross-discipline problem solving.
• Support customer-facing evaluations and pre-sales technical activities when needed.
• Assist integration, deployment, and post-delivery technical support for product teams.

Requirements

Must-have technical skills and professional capabilities.

• Strong expertise in SystemVerilog and Verilog RTL design.
• Extensive experience developing complex ASIC and/or FPGA logic (experience level specified in Education Requirements).
• Experience with industry-standard simulators such as Questa, Xcelium/Incisive, or VCS.
• Proficiency with scripting languages (Python, Perl, and/or Tcl).
• Deep understanding of digital design principles, micro-architecture, timing, and hardware implementation.
• Proven ability to analyze and resolve complex technical problems independently.
• Strong written and verbal communication and ability to collaborate across engineering teams.
• Track record of managing technical priorities and delivering designs on schedule.

Nice-to-have:

• Experience with memory controllers, high-performance interconnects, cache/coherency architectures, or data-center silicon.

Education Requirements

BSEE with 10+ years of relevant ASIC/FPGA logic design experience, or MSEE with 8+ years of relevant ASIC/FPGA logic design experience. Relevant fields include electrical/computer engineering or similar technical degrees related to digital/ASIC design.

About the Company

Company: KPG99

Technical staffing and recruiting firm that places contract engineering talent, including ASIC/SoC verification and other hardware and firmware roles.