Silicon Engineer II

Job Title

Silicon Engineer II

Role Summary

Join Microsoft's Compute Silicon & Manufacturing Engineering team to define and deliver manufacturing-ready silicon for Microsoft cloud infrastructure. The role focuses on implementation and signoff of partition-level RTL-to-GDSII flows to meet power, performance, area, and quality targets.

The position works within a hardware engineering organization supporting cloud servers and datacenter products; it requires close collaboration with RTL, CAD/PD methodology, and verification teams.

Experience Level

Mid-level — requires at least 6 years of professional semiconductor design experience.

Responsibilities

Primary responsibilities include executing implementation flows and driving closure for design partitions.

• Execute synthesis through place-and-route for assigned partitions and take designs to final signoff (timing, physical verification, EMIR, formal equivalence, low-power verification).
• Perform partition floorplanning and optimization for power, performance, and area.
• Run and evaluate PD flow flush / PD-TFM on partitions to identify flow issues early and coordinate fixes.
• Collaborate with PD flow/CAD and PD methodology teams to resolve tooling or methodology issues.
• Work with RTL designers to identify and resolve block closure issues affecting implementation.
• Use data-driven methods to understand tools, flows, and design methodology for construction, signoff, and optimization.
• Write and maintain scripts to automate implementation tasks and flows.

Requirements

Must-have skills and experience; preferred items noted separately.

• Minimum 6+ years in semiconductor design with proven experience implementing designs through synthesis, floorplanning, place-and-route, extraction, timing, and physical verification.
• Experience with timing signoff, STA, timing optimization, and timing closure.
• Practical floorplanning and PPA tradeoff experience for SoC/IP blocks.
• Familiarity with low-power design concepts, multi-voltage/multi-power-domain implementation, and UPF/LP methodologies.
• Strong scripting ability in one or more languages (Tcl, Perl); Python expertise is a plus.
• Good communication and collaboration skills; able to work across cross-functional teams.

Education Requirements

BS/BE/BTech or MS/ME/MTech in Electronics, Microelectronics/VLSI, Electrical Engineering, or related technical field (degrees listed in source). Equivalent technical experience may be considered.

Preferred

• Large SoC/CPU/IP tape-out experience at advanced foundry nodes.
• Hands-on experience with PD flows, PD-TFM setup, and flow bring-up.
• Experience with EDA tools such as Fusion Compiler, PrimeTime, StarRC, RedHawk, Formality, and formal equivalency checks (LEC).
• Experience with CTS techniques, power-grid planning (VA planning, secondary PG), signal integrity, and noise analysis.
• Project management skills and ability to manage multiple concurrent projects.

Additional Notes

This role requires meeting Microsoft security and export-control screening requirements, including verification of citizenship or residency documents.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.