Silicon Design-for-Test (DFT) Engineer

Job Title

Silicon Design-for-Test (DFT) Engineer

Role Summary

The DFT engineer will implement and verify design-for-test features for MatX silicon across compute, memory management, and high-speed connectivity IP in leading-edge process nodes. You will work with verification, firmware, and test engineering teams to develop test programs from simulation to ATE and to bring up production silicon.

Experience Level

Mid-level. The role expects hands-on DFT implementation experience; specific years of experience are not specified.

Responsibilities

Responsible for implementing and validating DFT and test flows for PHY and SoC blocks and supporting silicon bring-up.

• Design and develop test solutions for SERDES PHY: loopback, eye characterization, margin testing.
• Integrate DFT for PHY IP blocks: boundary scan, BIST interfaces, test-mode control signals; port test patterns from IP to SoC level.
• Develop and maintain firmware loading flows for PHY bring-up and test (SPI/JTAG-based firmware download, register initialization, debug support).
• Collaborate with verification, firmware, and test teams to develop ATE-ready test programs and bring-up silicon from simulation to lab.
• Execute block-level DFT insertion and verification: scan chain closure, ATPG pattern generation, and sign-off.
• Investigate test escapes and drive improvements to DFT coverage and test quality.

Requirements

Core technical skills and logistical requirements for the role.

• Must-have: Hands-on DFT implementation experience (MBIST, at-speed scan, scan compression).
• Must-have: Strong knowledge of DFT standards and protocols such as JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
• Must-have: Experience loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including bootloader and register initialization sequences.
• Must-have: Experience integrating PHY DFT interfaces (SERDES PHY test modes, analog test buses) into SoC DFT architecture.
• Required: Authorization to work in the United States and ability to work from the Mountain View office Tuesdays–Thursdays.
• Nice-to-have: System-level DFT access (hierarchical access, compression), multi-die/chiplet DFT experience, and familiarity with EDA DFT tools (Synopsys DFT Compiler, Mentor Tessent, ATPG tools).

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.