SiC Physical Design Manager

Job Title

SiC Physical Design Manager

Role Summary

Lead physical implementation for high-speed die-to-die interconnect chips (≥2 GHz) from RTL handoff through tape-out on advanced process nodes. Manage a global physical design team and coordinate with architecture, front-end, verification, and package teams to meet performance, SI/PI, and schedule targets.

The role emphasizes technical leadership in timing closure, floorplanning, power and clock tree synthesis, place-and-route, physical verification, and automation of flows using the Synopsys toolchain.

Experience Level

Senior-level — typically 10+ years of hands-on physical design experience, including leadership or management responsibility.

Responsibilities

Primary responsibilities include:

• Lead the complete physical design flow for high-speed interconnect chips from RTL handoff through tape-out.
• Drive floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification on 7nm, 5nm, and 3nm nodes.
• Own timing closure across corners and modes; resolve critical paths and ensure SI/PI integrity.
• Build, manage, and mentor a global physical design team; set technical direction and develop engineers at multiple levels.
• Collaborate with architecture, design, verification, and package teams to align implementation with product requirements and milestones.
• Champion automation and methodology improvements; develop and maintain Tcl/Python/Perl scripts and flow enhancements.
• Drive multiple successful tape-outs and establish best practices and tool flows across the organization.

Requirements

Must-have technical skills and experience:

• Deep expertise in high-frequency physical design and timing closure for multi-GHz designs.
• Proven experience delivering physical design on advanced nodes (7nm, 5nm, 3nm) with multiple tape-outs.
• Expert-level proficiency with Synopsys physical design tools: ICC2, Fusion Compiler, PrimeTime, StarRC, RedHawk.
• Strong scripting and automation skills in Tcl and Python; familiarity with Perl.
• Demonstrated experience managing and mentoring engineering teams across geographies.
• Ability to make timely trade-off decisions under schedule pressure and communicate technical tradeoffs to engineering and program management.

Nice-to-have:

• Experience with SI/PI at advanced nodes and high-bandwidth, low-latency interconnect designs.
• Experience shaping organization-wide physical design methodology and automation frameworks.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a strong plus.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.