Server Structural FEA Engineer

Job Title

Server Structural FEA Engineer

Role Summary

Senior individual-contributor role on Qualcomm's Data Center team responsible for structural integrity, reliability, and FEA of server SoCs and advanced semiconductor packages across package, board, and system integration.

Work closely with package, thermal, mechanical, electrical, manufacturing, reliability, and platform teams to develop predictive analyses, validate models, and translate results into actionable design guidance.

Experience Level

Senior - expects experienced candidate (typical guidance: 10+ years of advanced FEA experience in semiconductor packaging and structural reliability).

Responsibilities

Primary responsibilities include modeling, analysis, and cross-functional technical leadership to ensure package and platform structural reliability.

• Develop and apply advanced structural and thermo-mechanical FEA methods for SoC packages and package-to-platform interactions (CPI, warpage, stress, deformation).
• Analyze soldered and socketed packages under assembly, SMT, socket/retention, cooling, temperature cycling, qualification, and operating loads.
• Perform coupled structural-thermal analysis, contact/submodeling, nonlinear and viscoelastic simulations, and failure-mechanism modeling (fatigue, creep, fracture, delamination).
• Develop physics-based reliability and life-prediction models (solder/bump fatigue, die/BEOL stress, substrate/interposer cracking) and perform BLR/solder-joint reliability analyses.
• Conduct sensitivity, uncertainty, and bounding studies to quantify design margins and guide architecture decisions before hardware is available.
• Define model-validation and correlation strategies using material characterization, test vehicles, qualification data, and manufacturing feedback.
• Provide package mechanical properties, load limits, and failure criteria to system/platform analysis teams and translate simulation results into clear design requirements.

Requirements

Must-have technical skills, tools, and experience. Preferred items listed separately.

• 10+ years of advanced FEA experience in semiconductor packaging, microelectronics assembly, CPI, structural reliability, and interconnect technologies.
• Strong foundation in structural and failure mechanics, materials science, thermo-mechanical behavior, fatigue and creep, and nonlinear analysis.
• Proficiency with nonlinear FEA tools such as ANSYS Workbench, ANSYS APDL, ABAQUS, or equivalents.
• Experience modeling semiconductor-package failure mechanisms and correlating simulations with experimental, manufacturing, or qualification data.
• Experience with package-to-platform mechanical interaction (PCB, socket/retention, heatsink/cold plate, TIM materials) for high-pin-count server packages.
• Ability to develop predictive methodologies, perform sensitivity/uncertainty analysis, and produce repeatable workflows and validation frameworks.
• Proven ability to work independently, lead cross-functional technical alignment, and communicate results to engineering teams and leadership.

Education Requirements

Master's degree preferred; Bachelor's, Master's, or Ph.D. in Mechanical Engineering, Engineering Mechanics, Materials Science, Physics, Computer Engineering/Science, Information Systems, or a related technical field are cited in the posting. Equivalent practical experience may be accepted in lieu of degree per listed minimum-qualification alternatives.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.