Server CPU Physical Design Integration Engineer (Staff)
QualcommJob Title
Server CPU Physical Design Integration Engineer (Staff)
Role Summary
Join the Nuvia Data Center CPU team in Cambridge to lead physical design integration and verification for high-frequency, data-center CPU products. The role covers synthesis, floorplanning, partitioning, power and clock distribution, IP integration, signoff, and silicon validation.
Work closely with microarchitecture, RTL, CAD, circuit, block-level physical design, and SoC teams to deliver production-ready CPU designs.
Experience Level
Staff / Senior level. Typical experience guidance: Bachelor's +4 years, Master's +3 years, PhD +2 years in ASIC/CPU design or equivalent practical experience. Role expects technical leadership and cross-functional influence.
Responsibilities
Primary responsibilities include chip-level integration, layout, and closure for high-performance CPU designs.
- Own final CPU layout database implementation, integration, and verification for high-frequency CPU designs.
- Drive block partitioning, floorplanning, pin placement, and chip-level layout assembly.
- Integrate IP and coordinate with SoC and third-party IP teams to satisfy interface and integration requirements.
- Partner with CAD and physical design teams to develop, refine, and automate implementation and signoff flows.
- Perform timing closure, power and noise analysis, power integrity, and layout verification.
- Identify and resolve integration and tapeout issues and capture learnings for future product cycles.
- Provide technical leadership, mentor engineers, and influence cross-functional methodology (Staff-level responsibility).
Requirements
Must-have technical skills and experience for successful delivery.
- Deep CPU physical design implementation experience: synthesis, timing closure, multi-power-domain analysis, structured placement and routing.
- Experience with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.
- Hands-on experience developing and automating physical design methodologies and implementation flows.
- Strong scripting and automation skills (Python, TCL, Perl or similar) to improve productivity, debug efficiency, and design-flow scalability.
- Experience with floorplanning, partitioning, clock distribution, power planning, congestion analysis, and signoff closure.
- Experience collaborating with EDA vendors to optimize tool capabilities for high-speed, low-power CPU cores.
- For Staff-level: demonstrated ability to lead technical initiatives, mentor engineers, and define methodology across teams.
Nice-to-have: experience with advanced process nodes (7nm and below), hierarchical physical design methodologies, and integration of hard IP, memory macros, PLLs, and mixed-signal blocks.
Education Requirements
Required: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Typical experience guidance: Bachelor's +4 years, Master's +3 years, PhD +2 years in ASIC/CPU design, verification, validation, integration, or equivalent practical experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
