Server CPU Physical Design Engineer (Senior/Staff) - Cambridge, UK
QualcommJob Title
Server CPU Physical Design Engineer (Senior/Staff) - Cambridge, UK
Role Summary
Join the Nuvia Data Center CPU team in Cambridge to implement high-performance, power-efficient CPU cores. The role focuses on block implementation from RTL/netlist to GDS and close collaboration with architecture, RTL, circuit, CAD, SoC integration, timing, power, and post-silicon teams.
Position ranges from Senior to Staff; responsibilities scale with experience and may include technical leadership and mentoring.
Experience Level
Senior through Staff level. Indicative experience varies by grade; typical hires have several years of ASIC/physical design experience (roughly 1–5+ years depending on seniority). Staff-level candidates are expected to lead technical work and mentor others.
Responsibilities
Primary responsibilities include implementing CPU blocks, ensuring timing and PPA targets, and improving implementation flows:
- Implement RTL/netlist to GDS: synthesis, floorplanning, placement, clock tree synthesis, routing, ECOs, and signoff.
- Drive timing closure and convergence across multiple modes, corners, and operating conditions.
- Debug and resolve complex issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification.
- Collaborate with RTL, architecture, circuits, CAD, SoC integration, and post-silicon teams to improve quality and performance.
- Develop and enhance physical design flows, automation, and methodologies to improve productivity and results.
- Use data-driven analysis to identify bottlenecks and improve design convergence and PPA.
- For Staff level: provide technical leadership, define implementation strategies, and mentor engineers.
Requirements
Must-have technical skills and experience:
- Proven physical design implementation experience: synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signoff.
- Strong knowledge of static timing analysis and timing-closure methodologies, including trade-offs among timing, power, area, congestion, and routability.
- Hands-on experience with industry EDA tools such as Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal, or equivalents.
- Ability to debug complex physical-design issues across timing, congestion, clocking, routing, power, and verification domains.
- Scripting and automation experience in TCL, Python, or Perl.
- Effective communication skills for a global, cross-functional engineering environment.
Nice-to-have:
- Experience on CPU cores or other timing-critical, high-performance ASIC blocks.
- Experience with advanced process nodes (7 nm and below), low-power techniques, power-integrity/IR-drop analysis, timing ECOs, or methodology/automation development.
Education Requirements
The posting specifies degrees in Electrical Engineering, Computer Engineering, Computer Science, Science, Engineering, or a related technical field. Acceptable qualifications include a Bachelor's, Master's, or PhD, with indicative experience expectations tied to degree level (e.g., Bachelor's with ~2+ years, Master's with ~1+ year, or PhD); equivalent practical experience is accepted.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
