Server CPU Clock Physical Design Engineer (Staff)

Job Title

Server CPU Clock Physical Design Engineer (Staff)

Role Summary

Senior physical design engineer responsible for defining and implementing clock generation and distribution methodology for high-frequency data-center CPUs. The role partners with microarchitecture, RTL, CAD, circuit, block-level and top-level physical design teams to deliver low-skew, low-power, and signoff-ready clocking solutions.

This is a staff-level technical role with ownership of clocking methodology, implementation, analysis, and cross-functional leadership for next-generation CPU designs.

Experience Level

Level: Senior / Staff Engineer. Typical experience guidance: Bachelor's +4 years, Master’s +3 years, or PhD +2 years of relevant ASIC/CPU/physical-design experience; equivalent practical experience will be considered.

Responsibilities

Deliver clocking architecture, implementation, and validation across CPU designs and guide related teams.

• Define clock generation and distribution methodology for server-class CPU designs.
• Architect and implement low-skew, low-power clock networks (H-tree, mesh, spines, etc.).
• Collaborate with microarchitecture, RTL, CAD, circuit, block and top-level physical design teams to capture and satisfy clock requirements.
• Develop clock construction, analysis, and validation flows; drive methodology improvements.
• Use circuit-level simulation and analysis to validate clock circuits across PVT corners and operating modes.
• Analyze and debug clock-related timing, power, noise, variation, and implementation issues.
• Provide guidance on clock fixes, optimization opportunities, and signoff risks.
• For staff-level candidates: provide technical leadership, mentor engineers, and influence cross-functional methodology.

Requirements

Must-have technical skills and experience required to perform the role.

• Proven experience in construction and analysis of low-skew, low-power clock networks for high-frequency designs.
• Hands-on experience with clock distribution structures and methodologies (H-tree, mesh, spines).
• Strong knowledge of CTS, clock balancing, insertion delay, skew optimization, useful skew, and clock latency trade-offs.
• Understanding of device physics, RC delay, signal integrity, variation, and electrical effects on clock quality.
• Proficiency with SPICE simulation and circuit-level analysis for clock-path validation.
• Strong understanding of static timing analysis, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff interactions.
• Experience debugging clocking issues across timing, power, noise, variation, and circuit domains.
• Experience with industry-standard EDA implementation and signoff flows for physical design, timing and power analysis, and physical verification.
• Strong communication skills and ability to work effectively with global, cross-functional engineering teams.

Nice-to-have:

• Experience deploying clock methodology across multiple designs or technology generations.
• Experience with advanced process nodes (7nm and below), PLL modeling, jitter budgeting, and high-frequency CPU clocking.
• Experience with power-aware clocking (clock gating, resonant/mesh strategies) and clock power optimization.
• Scripting/automation experience (TCL, Python, Perl) for analysis and flow development.

Education Requirements

Required: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. Typical experience expectations: Bachelor’s +4 years, Master’s +3 years, or PhD +2 years in ASIC design, CPU design, physical design, clock design, or equivalent practical experience. Equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.