SerDes Validation Leader

Job Title

SerDes Validation Leader

Role Summary

Lead the physical-layer implementation, tuning, and post-silicon validation of ultra-high-speed SerDes links (112G and 224G PAM4). Coordinate cross-functional work with signal integrity, power integrity, hardware, and firmware teams to stabilize links on custom hardware platforms.

Experience Level

Senior (no specific years-of-experience listed).

Responsibilities

Primary responsibilities include SerDes bring-up, equalization tuning, lab characterization, and automation for repeatable validation.

• Drive implementation and register-level configuration of high-speed SerDes IP blocks on custom hardware systems.
• Own transceiver equalization tuning (CTLE, FFE, DFE) to maximize eye margin and minimize BER across cable, backplane, and board topologies.
• Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.
• Use BERTs, high-bandwidth oscilloscopes, pattern generators, and protocol analyzers to validate link performance and isolate issues.
• Collaborate with SI/PI, hardware, and firmware teams to correlate lab measurements with layout, simulation, and channel models.
• Develop and run script-based lab automation and Python-based test, measurement, and characterization workflows.
• Define and document best practices for SerDes bring-up, tuning, debug, and validation across hardware platforms.

Requirements

Must-have technical skills and experience for the role:

• Proven hands-on experience bringing up and validating 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces.
• Deep practical knowledge of SerDes implementation, configuration, equalization, and physical-layer debugging.
• Strong understanding of how TX/RX equalization settings affect signal integrity, jitter, eye margin, and BER.
• Advanced proficiency with high-speed lab equipment (BERTs, real-time or sampling oscilloscopes, pattern generators, protocol analyzers).
• Experience with automated, script-based testing and lab characterization-preferably using Python.
• Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions.
• Strong collaboration skills working with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.

Nice-to-have:

• Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments.
• Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols.
• Experience with SerDes IP from major commercial IP providers or custom in-house SerDes teams.
• Exposure to channel modeling, compliance testing, and production validation flows.

Education Requirements

Not specified.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.