Serdes PHY Analog Design Engineer
QualcommJob Title
Serdes PHY Analog Design Engineer
Role Summary
Design and deliver high-speed SerDes PHY analog circuits for SoCs, focusing on low-power analog solutions for advanced FinFET nodes. Work within a mixed-signal PHY team to perform architecture analysis, circuit design, verification, and post-silicon bring-up.
Experience Level
Senior - typically 8+ years of analog/mixed-signal design experience; lead candidates should have PHY lead and SoC integration experience.
Responsibilities
Primary responsibilities include hands-on analog design, verification, and integration of SerDes PHYs.
- Architect, design and optimize analog building blocks (LDOs, bias/reference, high-speed TX/RX: equalizer, sampler, serializer/deserializer).
- Design and analyze analog and digital PLLs for frequency synthesis and SerDes (charge pump, loop filter, VCO/DCO, PFD/TDC, high-speed dividers).
- Model PLL loop dynamics and jitter sources (RJ & DJ) and apply jitter analysis to design decisions.
- Perform schematic-to-post-layout verification and sign-off; support silicon bring-up and debug.
- Collaborate closely with RTL, digital design (DD), power (PD), design verification (DV), SoC verification, and post-silicon teams during integration.
- For lead roles: own PHY integration to SoC and coordinate with post-silicon teams (HSIO, ATE, SVE, CE) for validation and release.
Requirements
Must-have technical skills and experience; preferred items listed separately.
- Extensive hands-on analog circuit design experience in high-speed PHYs.
- Proven experience designing RX/TX building blocks (equalizer, sampler, deserializer) and power/reference circuits.
- Practical experience designing and tuning PLLs (including charge pump, VCO/DCO, PFD/TDC) and understanding jitter contributors.
- Experience with schematic-to-post-layout flow and post-silicon bring-up and debug.
- Proficiency with SPICE simulators and Cadence Virtuoso; experience with adexl is a plus.
- Scripting skills (Shell, Perl, Python) to automate design and verification tasks.
- Understanding of advanced FinFET process effects on circuit design and layout.
- Ability to work with global teams and communicate technical results clearly.
- Preferred: mixed-signal design background and familiarity with peripheral PHY protocols (USB, UFS, PCIe) and high-speed transceiver protocols.
Education Requirements
Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. Typical experience guidelines in the posting: Bachelor's +4 years, Master’s +3 years, or PhD +2 years of relevant hardware/analog engineering experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
