SerDes DSP System Architect
SynopsysJob Title
SerDes DSP System Architect
Role Summary
Lead system-level modeling and DSP algorithm development for high-speed SerDes transceivers (PAM4) used in PCIe and Ethernet products. Develop system simulations, correlate models with silicon measurements, and support lab validation.
Work closely with analog, digital, and hardware teams and provide system architecture guidance to R&D and customer teams to optimize performance, reliability, and time-to-market for wireline and optical serial links.
Experience Level
Senior-level; 10+ years of relevant experience in SerDes, DSP, or high-speed transceiver development.
Responsibilities
Core responsibilities include system modeling, simulation, algorithm design, silicon correlation, and cross-team technical support.
- Develop and maintain SerDes system models for PAM4 transceivers targeting PCIe (128+ Gbps) and Ethernet (200+ Gbps).
- Run system simulations to verify and sign off design performance across protocols and channels.
- Design and propose calibration and adaptation algorithms for transceivers.
- Correlate simulated performance with silicon measurements and lab data.
- Provide expert assistance to customers for system-level performance issues and troubleshooting.
- Collaborate with analog, digital, and hardware engineers through all development stages and post-silicon.
- Contribute to lab testing and analysis for high-speed serial links.
Requirements
Must-have technical skills and experience; nice-to-have items listed below.
- 10+ years of relevant experience in SerDes systems, DSP, or high-speed transceiver development.
- Strong experience modeling circuits and systems in MATLAB/Simulink.
- Solid understanding of DSP and communications theory, including equalization, encoding, and noise/crosstalk mitigation.
- Proficiency in analyzing link budgets for PAM4 high-speed serial links.
- Experience with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
- Familiarity with circuit topologies and Tx/Rx equalization techniques used in high-speed SerDes.
- Hands-on lab testing experience for high-speed serial links.
- Proficiency in C, Verilog-A, and SystemVerilog.
- Nice-to-have: Python programming and broader experience across wireline and optical applications.
Education Requirements
M.Sc. or Ph.D. in Electrical Engineering or Computer Engineering.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
