Senior VLSI Physical Design Engineer: Timing, Signoff & SI
Amaze SystemsJob Title
Senior VLSI Physical Design Engineer: Timing, Signoff & SI
Role Summary
Senior Physical Design Engineer responsible for driving physical implementation and signoff across the ASIC flow, from floorplanning through final signoff. Collaborates with logic design, synthesis, and verification teams to ensure designs meet timing, signal integrity, and manufacturability requirements.
Experience Level
Senior. Specific years of experience were not provided.
Responsibilities
Primary responsibilities cover physical implementation, timing closure, and signoff activities across multiple designs.
- Develop and execute floorplanning, placement, clock-tree synthesis (CTS), and routing strategies.
- Perform static timing analysis (STA) and drive timing closure to meet constraints.
- Lead signoff flows including DRC, LVS, antenna checks, and formal verification steps.
- Identify and mitigate signal integrity and power integrity issues.
- Collaborate with logic design, synthesis, and verification teams to ensure accurate physical-functional correlation.
- Prepare designs for manufacturing handoff and tapeout/signoff readiness.
Requirements
The source did not list detailed qualifications; below is a concise, role-focused summary consistent with the posting.
- Proven experience in physical design: floorplanning, placement, CTS, routing, and timing closure.
- Experience with signoff workflows and checks such as DRC, LVS, and antenna verification; familiarity with STA and SI issues.
- Demonstrated ability to drive closure across cross-functional teams (logic, synthesis, verification).
- Senior-level ownership of physical implementation through signoff.
- Nice-to-have: experience with production EDA signoff tools and tapeout flows (not specified in source).
Education Requirements
Not specified.
About the Company
Company: Amaze Systems
Headquarters: Redmond, WA, United States
A technology consulting firm based in Redmond, WA, providing engineering services in semiconductor design verification, embedded systems, and system-level testing. Specializes in verification leadership, UVM/SystemVerilog testbench development, and collaboration with design teams to deliver silicon-quality solutions.
