Senior VLSI Physical Design Engineer: Timing, Signoff & SI
Amaze SystemsJob Title
Senior VLSI Physical Design Engineer: Timing, Signoff & SI
Role Summary
Senior physical design engineer supporting the full silicon flow from floorplanning through signoff. The role works within the physical design team and collaborates with logic design, synthesis, and verification teams to ensure accurate physical and timing representation of designs.
Experience Level
Senior engineer. Specific years of experience not specified.
Responsibilities
Deliver physical design and signoff activities across multiple projects in the silicon implementation flow.
- Floorplanning and macro placement
- Standard-cell placement and legalization
- Clock tree synthesis (CTS) and clock planning
- Routing and timing closure
- Static timing analysis and signoff (timing closure)
- DRC, LVS and antenna checks
- Signal and power integrity (SI/PI) checks and mitigation
- Design-for-manufacturability (DFM) and ECO implementation
- Collaborate with logic, synthesis and verification teams; perform correlation and formal verification handoffs
Requirements
Core expectations for the role; hiring team did not list formal degree requirements in the posting.
- Proven senior-level experience executing physical design tasks through signoff (floorplan, placement, CTS, routing, timing closure)
- Experience with signoff flows, STA, and design rule checks
- Ability to collaborate with logic, synthesis and verification teams and drive closure across domains
- Strong troubleshooting and problem-resolution skills during late-stage implementation and signoff
- Clear written and verbal communication for cross-team coordination
Education Requirements
Not specified.
About the Company
Company: Amaze Systems
Headquarters: Redmond, WA, United States
A technology consulting firm based in Redmond, WA, providing engineering services in semiconductor design verification, embedded systems, and system-level testing. Specializes in verification leadership, UVM/SystemVerilog testbench development, and collaboration with design teams to deliver silicon-quality solutions.
