Senior Verification Manager, SERDES PHY

Job Title

Senior Verification Manager, SERDES PHY

Role Summary

Lead verification for flagship SERDES PHY IP, managing a distributed team of verification engineers and senior technical leads. Own verification sign-off quality across UVM simulation, mixed-signal co-simulation, emulation, and lab validation for high-speed serial PHYs.

Balance hands-on technical debugging and methodology development with people leadership, hiring, and mentorship to ensure release readiness and silicon correlation.

Experience Level

Senior — requires extensive hands-on mixed-signal verification experience (see Requirements). The posting specifies 10+ years of mixed-signal verification experience and 3+ years of people/team lead experience.

Responsibilities

The role combines technical leadership, hands-on debug, and ownership of verification sign-off:

• Lead and grow a distributed verification team and senior technical leads working on SERDES PHY mixed-signal verification.
• Debug priority regressions, customer escalations, and silicon correlation issues using SystemVerilog, UVM, co-simulation, and firmware bring-up flows.
• Own verification sign-off and release readiness: testplan review, coverage analysis, checker effectiveness, and release evidence documentation.
• Define and evolve UVM and mixed-signal co-simulation methodology, regression standards, reuse strategy, and automation frameworks.
• Partner with analog/digital design, firmware, and applications teams to close coverage gaps and resolve technical blockers.
• Represent verification in program reviews, customer technical engagements, and cross-functional release planning.
• Drive automation and AI-assisted regression triage to improve throughput, debug time, and coverage closure.

Requirements

Must-have technical and leadership qualifications; concise list of required and preferred skills.

• Must-have: 10+ years hands-on ASIC mixed-signal verification experience with recent activity in the past 3–5 years on debug, environment development, or sign-off.
• Must-have: 3+ years leading verification engineers or equivalent team-lead responsibilities (hiring, performance management, mentorship).
• Must-have: Deep experience with PCIe and/or Ethernet SERDES, high-speed serial links, DSP blocks, and clock/data recovery circuits.
• Must-have: Strong command of SystemVerilog, UVM, VIP integration, and coverage-driven verification methodology.
• Must-have: Proven mixed-signal verification flows including co-simulation, analog/digital modeling, and lab or silicon correlation.
• Must-have: Scripting proficiency in Shell, Perl, Python, or C++ to contribute to automation infrastructure.
• Must-have: Credible technical judgment under schedule pressure and ability to prioritize sign-off quality versus schedule risk.
• Nice-to-have: Experience with TX/RX PMA, common-mode PLLs, firmware bring-up, rate and power-state flows, and distributed team leadership with hands-on engagement.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.