Senior Verification Lead: SystemVerilog/UVM

Job Title

Senior Verification Lead: SystemVerilog/UVM

Role Summary

Lead verification engineering efforts for complex silicon projects, with primary responsibility for architecting and maintaining UVM-based testbenches and defining verification strategies.

Work on an onsite engineering team in Redmond, WA, collaborating with design teams to deliver high-quality verification environments and signoff-ready silicon.

Experience Level

Senior — expected experience level is senior engineering/lead (typically 7+ years of relevant verification experience).

Responsibilities

Core responsibilities for this role include:

• Define verification strategy and overall verification plan for assigned blocks or IP.
• Architect, develop, and maintain UVM/SystemVerilog testbenches and verification environments.
• Lead and mentor verification engineers; coordinate verification tasks and reviews.
• Collaborate with RTL designers to identify and close functional gaps and ensure design-for-testability.
• Drive functional coverage closure, bug triage, and root-cause analysis.
• Ensure use of appropriate verification methodologies, tools, and infrastructure for efficient regression runs.

Requirements

Must-have skills and experience; concise list of core requirements and useful additions:

• Expert in SystemVerilog and UVM with a track record of architecting and maintaining UVM testbenches.
• Proven experience leading verification teams and coordinating cross-functional verification activities.
• Strong hands-on verification experience: writing tests, constraints, sequences, and driving coverage closure.
• Solid knowledge of AMBA protocols (AXI, AHB, APB) and experience verifying protocol-compliant IP or subsystems.
• Experience collaborating with RTL designers and participating in design reviews and debug sessions.
• Nice-to-have: experience with simulation tools (Synopsys VCS, Cadence Xcelium/Incisive), scripting (Python, Perl, Tcl), and CI/infrastructure for regressions.

Education Requirements

Not specified.

About the Company

Company: Amaze Systems

Headquarters: Redmond, WA, United States

A technology consulting firm based in Redmond, WA, providing engineering services in semiconductor design verification, embedded systems, and system-level testing. Specializes in verification leadership, UVM/SystemVerilog testbench development, and collaboration with design teams to deliver silicon-quality solutions.