Senior Verification Lead — SystemVerilog/UVM
Amaze SystemsJob Title
Senior Verification Lead — SystemVerilog/UVM
Role Summary
Lead verification activities for silicon projects, owning UVM testbench architecture and verification strategy. Work closely with RTL designers and cross-functional teams to ensure timely, high-quality delivery of IP/SoC blocks. Onsite role based in Redmond, WA.
Experience Level
Senior-level. Title indicates senior responsibility; no specific years of experience were provided.
Responsibilities
Primary responsibilities include:
- Architect, develop, and maintain SystemVerilog/UVM testbenches and verification environments.
- Define verification strategies, plans, metrics, and schedules for IP/SoC verification.
- Lead, mentor, and coordinate verification engineers and team activities.
- Collaborate with RTL designers to plan coverage closure, debug issues, and verify fixes.
- Manage regression suites, run regressions, analyze results, and drive corrective actions.
- Ensure verification quality and efficiency across the silicon development lifecycle.
Requirements
Must-have skills and experience:
- Strong hands-on experience with SystemVerilog and UVM.
- Proven experience leading verification teams and verification projects.
- Deep understanding of AMBA protocols (for example AXI/AHB).
- Experience defining verification strategy, creating plans, and driving coverage closure.
- Practical experience with verification flows, simulators, and regression automation.
- Effective collaboration and communication with design and cross-functional teams.
Nice-to-have:
- Experience with formal verification, emulation, or hardware-assisted verification.
- Familiarity with CI systems and coverage analysis tools.
Education Requirements
Not specified.
About the Company
Company: Amaze Systems
Headquarters: Redmond, WA, United States
A technology consulting firm based in Redmond, WA, providing engineering services in semiconductor design verification, embedded systems, and system-level testing. Specializes in verification leadership, UVM/SystemVerilog testbench development, and collaboration with design teams to deliver silicon-quality solutions.
