Senior Verification Engineer — VLSI/UVM, SystemVerilog

Job Title

Senior Verification Engineer — VLSI/UVM, SystemVerilog

Role Summary

Senior verification role based in Austin, TX. You will plan and perform functional verification of digital VLSI blocks, develop SystemVerilog/UVM environments and testbenches, and work closely with RTL designers to achieve verification closure.

Experience Level

Senior — requires at least 6 years of verification experience as specified in the posting.

Responsibilities

Key responsibilities include:

• Develop and execute verification plans for digital design blocks.
• Design and implement SystemVerilog/UVM testbenches and verification environments.
• Create and run regression suites and coverage-driven tests.
• Debug functional failures and collaborate with design engineers to resolve issues.
• Maintain verification infrastructure and automation for efficient regressions.
• Mentor junior verification engineers and review verification deliverables.

Requirements

Essential and preferred qualifications:

• Must-have: Minimum 6 years of verification experience; strong SystemVerilog and UVM experience; deep understanding of verification flows and methodologies.
• Preferred: Experience with Ethernet protocols.
• Work arrangement: On-site in Austin, TX — five days per week.
• Good collaboration and communication skills to work with design teams.

Education Requirements

Not specified.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.