Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Senior individual-contributor focused on functional verification of cache and memory-subsystem features with emphasis on cache coherency, ordering, correctness, and subsystem integration. The role sits on the horizontal cache verification team and works closely with architecture, design, and verification stakeholders to deliver signoff-quality verification.

Experience Level

Senior — 3+ years of relevant functional verification experience (IP, subsystem, or SoC verification).

Responsibilities

Primary responsibilities include designing and executing verification plans, building robust environments, and driving issue resolution across RTL and testbench components.

• Create verification strategies and test plans for cache and memory-subsystem areas.
• Develop and maintain UVM/SystemVerilog environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Implement directed and constrained-random tests targeting coherency, ordering, concurrency, backpressure, and error scenarios.
• Analyze failures, isolate root causes, and coordinate fixes across RTL, testbench infrastructure, and test content.
• Write and analyze functional coverage; close coverage holes to reach signoff criteria.
• Contribute methodology, automation, and debug improvements to increase team productivity and reuse.

Requirements

Must-have:

• 3+ years of IP, subsystem, or SoC functional verification experience, preferably in CPU, memory-system, or cache verification.
• Strong hands-on experience with SystemVerilog and UVM.
• Solid understanding of computer architecture and memory-system behavior, including cache coherency and ordering concepts.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Strong problem-solving skills and ability to work across design and verification teams.

Nice-to-have:

• Direct experience verifying cache or memory-subsystem functionality in multicore systems.
• Experience with subsystem integration and protocol interactions across multiple interfaces.
• Scripting and automation experience (Python or similar).
• Familiarity with formal verification, performance-oriented verification, or emulation/FPGA-assisted debug.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.