Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

Join NVIDIA's Display Team to verify GPU and SoC display engines used across consumer, professional, automotive, and AI products. The role owns verification testplan development, verification sign-off, and infrastructure delivery while partnering with architects and ASIC engineers.

This position emphasizes scalable UVM-based verification infrastructure, coverage-driven closure, and cross-site collaboration to deliver silicon-quality IP.

Experience Level

Senior — 10+ years of relevant verification or related engineering experience.

Responsibilities

Primary responsibilities include planning and executing functional and performance verification for display IP, building infrastructure, and driving sign-off.

• Define verification scope and develop functional and performance testplans.
• Design and implement scalable UVM-based testbenches, checkers, and C/C++ test harnesses.
• Leverage agentic AI to automate repetitive tasks, accelerate debug, and increase team efficiency.
• Create constrained-random stimulus, track functional coverage, and drive coverage closure.
• Debug complex RTL, software-model mismatches, and system integration issues across tools and sites.
• Partner with architects and ASIC engineers to validate architectural and micro-architectural decisions.
• Collaborate with global teams, external partners, and customers to deploy verification flows and ensure consistent IP behavior.

Requirements

Must-have technical skills, domain knowledge, and professional capabilities for successful performance in this role.

• 10+ years of hands-on verification experience in silicon/firmware/RTL verification.
• Proficiency in UVM, SystemVerilog, Verilog, Python, and C/C++ for verification and debug.
• Experience with constrained-random stimulus, functional coverage, and assertion-based verification.
• Familiarity with industry EDA tools such as VCS, Verdi/Debussy, and standard debuggers (e.g., GDB).
• Strong software engineering practices: readable/maintainable code, version control, and code review.
• Domain knowledge of display pipelines and relevant protocols, and system low-power features (clock gating, power domains, retention sequences).
• Proven ability to independently investigate unfamiliar sub-blocks, communicate clearly across time zones, and work with cross-functional teams.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field — or equivalent practical experience.

Nice-to-have

Additional experience that strengthens candidacy.

• Prior display unit verification: pixel processing, ISO performance testing, and HLS-based designs.
• Hands-on verification of display protocols end-to-end and MMU/SMMU behavior under ISO traffic.
• Experience shaping architectural specifications and micro-architecture decisions.

Compensation

Base salary ranges: 168,000 USD - 264,500 USD (Level 4); 196,000 USD - 310,500 USD (Level 5). Final base pay depends on location, experience, and internal pay bands.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.