Senior Verification Engineer

Job Title

Senior Verification Engineer

Role Summary

The Senior Verification Engineer will own verification architecture and implement verification environments for block-level, subsystem and SoC designs. The role partners with RTL designers and system architects to deliver verification assets that meet content, performance, quality and schedule objectives.

Experience Level

Senior — expects experienced verification engineers with significant ASIC/SoC verification background (see Education Requirements for specific years-of-experience guidance).

Responsibilities

Primary responsibilities focus on planning, implementing and validating verification environments and running simulations for SoC projects.

• Define verification strategies, methodologies and the simulation environment for blocks and SoC top level.
• Collaborate with RTL designers, system architects and block-level verification engineers to derive top-level verification requirements and test plans.
• Develop, maintain and publish verification specifications and test plans.
• Implement verification environments using industry methodologies (UVM/OVM/SystemVerilog/Vera) and create directed and constrained-random tests.
• Run simulations, analyze and debug simulation failures; run and debug gate-level simulations.
• Generate and review code coverage and functional coverage reports.
• Implement constraint- and assertion-based verification and integrate assertions into the verification flow.
• Automate simulation and reporting flows using scripting.

Requirements

Must-have technical skills and tools for the role.

• Must-have: Proven ASIC/SoC verification experience and familiarity with verification methodologies.
• Must-have: Proficiency in UVM, OVM, SystemVerilog, Vera and Verilog.
• Must-have: Experience with sign-off simulators and debug tools; familiarity with Verdi or Siloti.
• Must-have: Experience writing test plans and creating directed and constrained-random test cases; working with code and functional coverage.
• Must-have: Strong scripting skills (Perl, Python, Linux shells) to automate verification flows.
• Nice-to-have: Prior experience with SoC top-level integration verification and extensive gate-level simulation debugging.
• Nice-to-have: Experience with assertion-based verification methodologies.

Education Requirements

Bachelor of Science in Electrical Engineering (BS/BE) with 3+ years of relevant verification experience, or Master of Science in Electrical Engineering (MS/MTech) with 1+ year of relevant verification experience.

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.