Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

Senior verification engineer on Draper's Digital Design Team responsible for planning and executing verification for FPGA and ASIC digital and mixed-signal designs across embedded security, cryptography, signal and image processing, navigation, and communications domains.

Own verification strategies, lead small teams, and collaborate with multidisciplinary engineers to close functional and code coverage using UVM, formal tools, and simulation environments.

Experience Level

Senior — typically 5–7 years of relevant systems analysis or digital verification experience.

Responsibilities

Primary duties include defining and executing verification activities and guiding less-experienced engineers.

• Develop verification strategies and author/execute verification plans for block and chip-level designs.
• Design and implement UVM agents and testbenches; integrate VIPs for industry-standard buses.
• Instantiate and run block-level and chip-level UVM/UVMF environments; close code and functional coverage.
• Implement covergroups per design requirements and drive coverage closure to meet goals.
• Use formal analysis tools to supplement simulation-based verification.
• Work with RTL designers to debug simulations, resolve issues, and suggest design changes when appropriate.
• Perform code reviews, mentor junior engineers, and lead small teams toward program goals.
• Identify program/system-level technical risks and develop mitigation strategies.
• Integrate verification and modeling tools with other simulation flows and automation scripts.

Requirements

Must-have technical skills and experience; familiarity with listed tools and methodologies is required.

• Must-have: Fluent in SystemVerilog including SVA; recent, practical experience with UVM/UVMF.
• Must-have: Experience with at least one major industry simulator (Questa, Xcelium, VCS).
• Must-have: Strong experience with constrained-random testing and coverage-driven verification.
• Must-have: Experience with DDR3/DDR4 and AMBA AXI protocols; familiarity with IEEE bus standards.
• Must-have: Practical use of formal analysis tools as part of verification flows.
• Must-have: Scripting skills (Python, Perl, Bash or similar) and ability to work in Linux-based environments.
• Must-have: Strong analytical, communication, and organization skills; ability to collaborate across multidisciplinary teams.
• Must-have: Ability to obtain and maintain a government security clearance.
• Nice-to-have: Prior experience in embedded security, cryptography, signal/image processing, navigation, or communications verification.
• Nice-to-have: Experience integrating descriptive modeling tools with other simulation tools.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or other relevant engineering field required. Master's degree preferred.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.