Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

Senior engineer on Draper’s Digital Design Team responsible for developing and executing verification strategies for FPGA and ASIC designs. Work focuses on UVM-based verification, coverage-driven and constrained-random testing, and formal analysis for designs in embedded security, cryptography, signal/image processing, navigation and communications.

Experience Level

Senior-level. Role requires approximately 5–7 years of relevant systems analysis or digital verification experience.

Responsibilities

Design and execute verification approaches across block- and chip-level environments and contribute to system-level decisions.

• Develop verification and test plans and author UVM testbenches (agents, sequences, scoreboards).
• Instantiate and integrate VIP for industry-standard buses and proprietary bus agents.
• Execute simulations, debug RTL issues with designers, and close functional and code coverage to target level.
• Implement cover groups and coverage-driven verification strategies; perform constrained-random testing.
• Apply formal analysis tools and techniques to verify design correctness.
• Perform code reviews, lead small teams, and mentor junior engineers.
• Identify program/system-level technical risks and develop mitigation strategies.
• Translate requirements into verification architecture and contribute to integration and test activities.
• Use scripting to automate flows and work in Linux-based environments.

Requirements

Core technical skills and demonstrated hands-on verification experience are required.

• 5–7 years of experience in digital verification or systems analysis.
• Fluent in SystemVerilog, including SVA; recent, hands-on experience with UVM/UVMF.
• Experience with at least one major industry simulator (QuestaSim, Xcelium, VCS).
• Familiarity with bus protocols such as DDR3/DDR4 and AMBA AXI.
• Strong grasp of constrained-random testing and coverage-driven verification methodologies.
• Practical experience with formal verification tools and methodologies.
• Proficiency with scripting languages (Python, Perl, Bash) to automate verification flows.
• Ability to work in Linux and integrate simulation and modeling tools.
• Strong analysis, problem-solving, written and verbal communication skills; ability to present results to stakeholders.
• Demonstrated ability to lead small teams and mentor junior staff.
• Must have or be able to obtain and maintain a U.S. government security clearance.
• Nice-to-have: experience with FPGA verification, embedded security or cryptography, signal/image processing domains.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or another relevant engineering field is required. Master’s degree is preferred.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.