Senior UVM Digital Verification Engineer

Job Title

Senior UVM Digital Verification Engineer

Role Summary

Senior verification engineer on Draper’s Digital Design Team responsible for developing and executing verification strategies for FPGA and ASIC designs across embedded security, cryptography, signal/image processing, navigation, and communications domains.

Work with multidisciplinary teams to translate requirements into verification architectures, drive closure on functional and code coverage, and apply formal analysis where applicable.

Experience Level

Senior level. The posting requests approximately 5–7 years of relevant experience in systems analysis, digital verification, or related engineering roles.

Responsibilities

Primary responsibilities include planning and executing verification activities and leading small teams to deliver verified digital hardware designs.

• Develop verification strategies, author and execute verification plans for block- and chip-level designs.
• Design and implement UVM agents and testbenches; instantiate VIPs for standard buses.
• Apply constrained-random testing and coverage-driven verification to achieve closure.
• Use formal analysis tools and integrate descriptive models with other simulation tools.
• Perform RTL debug with designers to resolve simulation issues and perform code reviews.
• Implement SVA cover groups and drive code/functional coverage to target levels.
• Identify system-level technical risks and develop mitigation strategies.
• Lead and mentor junior engineers; contribute to task planning and technical decisions.
• Collaborate with cross-disciplinary teams and external partners to meet program goals.

Requirements

Must-have qualifications and technical skills for daily execution of the role.

• Must-have: Fluent in SystemVerilog (including SVA) and recent experience with UVM/UVMF.
• Must-have: Experience with at least one major industry simulator (QuestaSim, Xcelium, or VCS).
• Must-have: Strong grasp of constrained-random testing and coverage-driven verification; experience achieving coverage closure.
• Must-have: Practical experience with formal analysis tools.
• Must-have: Experience with DDR3/DDR4 and AMBA AXI or similar bus protocols.
• Must-have: Scripting skills (Python, Perl, Bash or similar) and ability to work in a Linux environment.
• Must-have: Strong analysis, problem-solving, communication, and organizational skills.
• Must-have: Ability to obtain and maintain a U.S. government security clearance (or already cleared).
• Nice-to-have: Familiarity with additional IEEE bus standards and multi-domain modeling/integration experience.

Education Requirements

Bachelor's degree in Aerospace, Electrical, Mechanical, or another relevant engineering field is required. A Master's degree is preferred.

About the Company

Company: Draper

Headquarters: Cambridge, MA, United States

Draper is an independent, nonprofit research and development organization based in Cambridge, Massachusetts. With over 2,000 employees, Draper develops advanced technologies in defense, space, biomedical engineering, and other national-security and commercial domains through multidisciplinary teams of engineers and scientists.