Senior Timing Engineer

Job Title

Senior Timing Engineer

Role Summary

Work on timing sign-off, library characterization and related CAD flows for ASIC/SoC development in Qualcomm's ASICS Engineering team. The role focuses on timing analysis, library characterization, correlation to circuit-level simulation, automation of flows, and collaboration with physical design and verification teams.

Experience Level

Senior level. Preferred experience indicated at 3+ years in ASIC-related roles; minimum experience varies by degree (see Education Requirements).

Responsibilities

Primary responsibilities include timing, characterization and cross-team delivery for IP and SoC blocks.

• Perform timing sign-off activities and static timing analysis (STA) for blocks and SoCs.
• Develop and validate standard-cell library characterization and library flows.
• Correlate timing sign-off tools with SPICE simulations across metrics such as timing, noise and Monte Carlo.
• Implement and maintain flows for LVF, AOCV/POCV/SOCV and related timing checks.
• Work with extraction, modelling and aging/reliability models for advanced technology nodes.
• Collaborate with physical design (place-and-route), RTL and verification teams to meet system requirements.
• Write technical documentation for EDA/IP/ASIC projects and present findings to stakeholders.

Requirements

Key technical skills and practical experience required. Degree and formal education details are listed in Education Requirements below and have been omitted from this section.

Must-have:

• Extensive hands-on experience in timing activities (library, LVF, AOCV/POCV/SOCV, STA sign-off).
• Experience with CAD/EDA tools and correlating sign-off results to SPICE simulations.
• Practical experience in standard-cell library characterisation and characterization flows.
• Strong scripting and automation skills (Python, Perl, TCL, Bash or similar) to develop and improve flows.
• Working knowledge of SPICE extraction, device modelling and aging/reliability effects for advanced nodes.
• Understanding of physical design flows (place-and-route) and how they impact timing and power.
• Ability to develop and validate new methodologies and work across cross-functional teams.

Nice-to-have:

• Experience with architecture and design tools and with design verification methods.
• Prior experience in ASIC/IP design projects in a commercial environment.

Education Requirements

Bachelor's, Master's or PhD in Science, Engineering, Electrical/Electronic Engineering, Computer Engineering, Computer Science or a related technical field are mentioned. Minimum-qualification guidance in the source: Bachelor + 2+ years ASIC-related experience, or Master + 1+ year, or PhD (experience may vary). The posting also states applications with equivalent practical experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.