Senior Test Engineer

Job Title

Senior Test Engineer

Role Summary

Join Microsoft SCHIE (Silicon, Cloud Hardware, and Infrastructure Engineering) within Compute Silicon & Manufacturing Engineering to develop and validate test solutions for cloud-scale ASICs. The role focuses on scan/structural test, ATE program development, silicon bring-up, and manufacturing readiness for high-performance and AI-oriented chips.

Experience Level

Senior — typically requires multiple years of IC/test engineering experience; posting preference is for candidates with roughly 5+ years in product and test engineering or equivalent experience.

Responsibilities

The role is an individual contributor responsible for test engineering across pre-silicon, silicon bring-up, and manufacturing phases.

• Develop and support scan (structural) test strategies, ATPG pattern integration, and pattern validation.
• Create, bring up, and debug ATE test programs; perform silicon characterization and yield analysis for logic defects.
• Support silicon bring-up, validation, and manufacturing readiness with cross-functional teams (design, DFT, product, manufacturing).
• Apply DFT/scan features (SAF/TDF), JTAG/boundary scan, and at-speed testing in test flows.
• Use diagnosis tools for failure analysis and to drive yield-improvement actions.
• Work with simulation/emulation and pattern verification teams to validate scan test content.
• Execute test plans, identify issues, and escalate risks with clear technical data and metrics.
• Participate in product qualification and reliability activities for silicon and packaged parts.

Requirements

Must-have technical skills and job conditions; preferred items listed separately.

• Hands-on experience with ATE test program development, bring-up, and debug for scan/structural test.
• Practical knowledge of DFT concepts, scan architecture, ATPG flows, and scan fault models (stuck-at, transition).
• Experience with silicon bring-up, post-silicon debug, characterization on ATE platforms (e.g., Advantest 93K) and yield analysis.
• Proficiency with scan diagnosis tools and techniques for failure localization and yield improvement.
• Strong troubleshooting, test debugging, and data-driven problem solving skills; ability to present technical data clearly.
• Proficiency in Linux-based environments and experience with unit/integration test practices.
• Willingness to work on-site under a hybrid schedule (3 days/week in-office) and to travel approximately 25–50% as required.
• Ability to meet Microsoft security and export-control screening requirements (background check; verification of citizenship/residency for access to export-controlled information).

Nice-to-have:

• Experience with complex SoCs, high-performance/AI designs, advanced-node chips, or mixed-signal IP test interactions.
• Familiarity with statistics, DOE, basic device physics, and fundamentals of computer architecture.
• Experience optimizing ATPG patterns, validation flows, and test program performance.

Education Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field with 1+ year technical engineering experience; OR Masters Degree in those fields with 4+ years; OR Bachelors Degree in those fields with 5+ years; OR equivalent practical experience. Fields cited include EE, CE, CS or related technical disciplines. The posting also requires verification of citizenship or U.S. residency as part of export-control eligibility screening.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.