Senior Technical Staff Engineer - Design

Job Title

Senior Technical Staff Engineer - Design

Role Summary

Senior technical leader for Microchip's Data Center Solutions (DCS) business unit, responsible for architecture and implementation of data-center class ASICs and complex IPs. The role focuses on high-performance RTL design, micro-architecture, and cross-functional delivery for server, storage, and accelerator applications.

Experience Level

Senior — requires extensive industry experience; posting specifies 15+ years of ASIC or SoC digital design experience.

Responsibilities

Accountable for architecture, design quality, and delivery of complex digital subsystems and full chips for data center workloads.

• Lead architecture and micro-architecture definition for complex IPs, subsystems, or full-chip designs.
• Drive end-to-end RTL design execution from concept through synthesis, sign-off, and silicon bring-up support.
• Serve as a technical authority for digital design, ensuring quality, performance, power, and area (PPA).
• Diagnose and resolve complex cross-domain design and EDA tool challenges affecting schedule or silicon quality.
• Collaborate with verification, physical design, DFT, system, and product teams for robust delivery.
• Define low-power, high-performance design strategies suitable for data center workloads.
• Influence protocol and platform roadmap decisions for PCIe, CXL, NVMe, SAS and related interconnects.
• Mentor and guide senior and staff engineers; conduct architectural reviews and provide design direction.
• Represent the design organization in technical reviews with senior leadership and cross-functional stakeholders.
• Promote data-driven approaches and AI/ML-assisted automation to improve design quality and time-to-market.
• Define and enforce design methodologies, sign-off criteria, and best practices across projects.

Requirements

Must-have technical skills and experience for immediate contribution.

• 15+ years of experience in ASIC or SoC digital design.
• Strong expertise in SystemVerilog RTL design and micro-architecture development.
• Proven track record delivering multiple complex tape-outs in high-performance or data center–class silicon.
• Hands-on experience with lint, CDC, formal verification, logic synthesis, and static timing analysis.
• Solid understanding of physical design interactions, including timing, power, and congestion considerations.
• Experience with low-power design methodologies and flows.
• Mandatory knowledge of DFT, including scan, testability considerations, and DFT sign-off interactions.
• Proficiency in scripting languages such as Tcl, Perl, and/or Awk.
• Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, SAS/SATA, or similar serial interfaces.
• Willingness to travel up to 25%.
• Nice-to-have: Hands-on experience with Cadence-based ASIC design environments.

Education Requirements

Bachelor's degree in Electronics or Electrical Engineering is required.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.