Senior System Integration Engineer, Memory

Job Title

Senior System Integration Engineer, Memory

Role Summary

Lead system-level memory integration and bringup for HBM and LPDDR in next-generation SoCs. The role spans silicon, package, firmware, validation, and product teams to deliver signed-off memory operating points and reliable behavior at production scale.

Embedded in NVIDIA's Silicon Co-Design Group (ArchDev), you will own characterization, margining, debug, and closure for memory subsystems that determine product performance, power, and reliability.

Experience Level

Senior — requires extensive hands-on experience (guidance: 12+ years) in HBM, LPDDR, or other high-speed memory systems, including silicon bringup and characterization at scale.

Responsibilities

Primary responsibilities include bringing memory subsystems from first silicon to production readiness and establishing robust characterization and release criteria.

• Drive HBM and LPDDR system integration, bringup, characterization, and debug for SoC programs from first silicon to production.
• Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware.
• Lead post-silicon margining, VF shmoo, eye measurements, and correlation across voltage, temperature, and frequency.
• Debug memory training, calibration, signal/power integrity (SI/PI), and system-level stability issues.
• Define validation and characterization plans, specify tests and data collection, and track issues to closure with sufficient fidelity for program decisions.
• Collaborate cross-functionally with design, package, firmware, validation, and product teams to translate characterization into signed-off operating points.
• Improve test sequencing, automation, and data analysis to accelerate time from silicon arrival to production-ready results.

Requirements

Concise list of must-have skills and preferred qualifications.

• Must-have: 12+ years of hands-on experience with HBM, LPDDR, or high-speed memory systems, including silicon bringup, characterization, and debug at scale.
• Must-have: Deep understanding of SI/PI, timing, margining, memory training behavior, and post-silicon margining techniques (VF shmoo, eye, correlation).
• Must-have: Proven ability to lead cross-functional technical efforts and communicate trade-offs across design, package, firmware, validation, and product teams.
• Nice-to-have: PHY and controller development experience.
• Nice-to-have: Experience with HBM3/HBM3E specifics, JEDEC margin practices, thermal-electrical co-simulation, ECC methods, and power-management strategies.
• Nice-to-have: Familiarity with LLM/ML-assisted debug, automated test sequencing, and data-driven characterization workflows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering — or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.