Senior Static Timing Analysis (STA) Methodology Engineer

Job Title

Senior Static Timing Analysis (STA) Methodology Engineer

Role Summary

Join the ASIC design team to lead STA methodology and timing-closure efforts across multiple IPs, projects, and technology nodes for SoC designs targeting 5G, IoT, and LEO satellite communications. You will own production STA flows, drive signoff closure, and introduce automation and data-driven improvements to PPA and team productivity.

Experience Level

Senior — requires 8+ years of industry experience in STA and timing methodology.

Responsibilities

Primary responsibilities center on developing, operating, and improving STA flows and methodologies, and providing technical leadership across teams.

• Lead cross-functional timing efforts across IPs, projects, and technology nodes.
• Develop and enhance STA methodology across the RTL-to-GDS flow: early timing estimation, synthesis and P&R optimization, signoff criteria, and post-route ECO strategies.
• Architect, optimize, and maintain production STA flows using industry-standard EDA tools to improve PPA and runtime efficiency.
• Drive signoff correlation and closure using PrimeTime and related tools (PT-SI, PTPX, PT-ECO).
• Debug timing constraints, resolve correlation issues, and implement timing-closure strategies.
• Explore and deploy data-driven or ML-assisted techniques to automate STA, predict timing risk, and prioritize optimization.
• Design, implement, and maintain scalable CAD utilities and flow components (scripting, automation).
• Continuously refine workflows and introduce new technologies to ensure robust, PPA-optimized timing solutions.
• Provide mentorship and timing-closure guidance to RTL and physical design engineers.

Requirements

Must-have technical skills and experience for this role.

• 8+ years of industry experience in STA and timing methodology focused on high-performance and low-power designs at advanced nodes.
• Deep knowledge of STA techniques including noise, crosstalk, OCV/AOCV/POCV, and LVF analysis.
• Extensive hands-on experience with PrimeTime and signoff toolflows (PT-SI, PTPX, PT-ECO) and driving signoff correlation.
• Experience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques.
• Proficiency in writing production-quality scripts for CAD utilities and flows (Tcl, Python, and/or Perl).
• Solid understanding of clock tree synthesis (CTS) and its interaction with timing analysis.
• Strong communication and collaboration skills for cross-functional, multi-project environments.

Preferred:

• Experience with advanced process nodes (7nm, 5nm, or below).
• Familiarity with low-power methodologies (DVFS, power gating) and their timing implications.
• Exposure to interface protocol timing (DDR, PCIe, USB, SerDes).
• Experience applying ML or data-driven methods to EDA flow optimization.
• Background in satellite communications, 5G, or IoT SoC design.

Education Requirements

BS or MS in Electrical or Computer Engineering, or equivalent industry experience.

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.