Senior Static Timing Analysis (STA) Engineer

Job Title

Senior Static Timing Analysis (STA) Engineer

Role Summary

Senior engineer responsible for static timing analysis and timing closure for complex SoC designs. Partner with architecture, logic, clocking, DFT, and physical design teams to ensure timing convergence, signal integrity, and performance targets are met.

Contribute to methodologies, tools, and flows used across advanced SoC programs and influence timing/modeling practices for production chips.

Experience Level

Senior — typical experience expectations: generally 6+ years industry experience (for candidates without an advanced degree); specific education-to-experience tradeoffs are listed under Education Requirements.

Responsibilities

Primary hands-on and technical leadership responsibilities include:

• Perform SoC-level static timing analysis and timing optimization to meet functional and performance requirements.
• Create and verify timing constraints; identify and fix timing violations at block and chip level.
• Execute timing rollups and develop optimized clock networks for performance and power.
• Define methodologies and produce high-quality timing models to enable efficient physical design execution.
• Establish appropriate PVT (process, voltage, temperature) conditions and align timing analysis with product plans and binning strategies.
• Collaborate with clocking, physical design, DFT, architecture, and logic teams to balance fixes across timing, power, and partitioning.
• Contribute to tool, flow, and methodology development to improve SoC physical design and timing processes.
• Mentor peers and provide technical leadership across multi-disciplinary teams.

Requirements

Must-have technical skills and professional capabilities:

• 6+ years industry experience in STA and SoC timing (or equivalent industry experience consistent with senior level).
• Demonstrated experience with SoC-level static timing analysis, clock network design, and timing closure methodologies.
• Proficiency with timing constraint creation/adaptation and timing budgeting processes.
• Practical knowledge of physical design flows and optimization techniques used for timing closure.
• Experience with industry-standard tools for timing analysis, extraction, and physical design.
• Scripting experience (TCL) for automation of timing and flow tasks.
• Strong technical leadership, cross-functional collaboration, and communication skills.
• Ability to define and improve methodologies, mentor engineers, and drive technical decisions.

Nice-to-have:

• DFT architecture experience and familiarity with SoC clocking methodologies.
• Experience developing timing models and flow automation for large-scale SoC projects.

Education Requirements

Bachelor's degree in Computer Engineering, Computer Science, or a related STEM discipline with 6+ years industry experience; OR Master's degree in the same fields with 4+ years industry experience. A PhD in a related field with 2+ years experience is listed as a preferred qualification.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.