Senior Staff Verification Engineer (Worldguard)
SiFiveJob Title
Senior Staff Verification Engineer (Worldguard)
Role Summary
Lead verification of the Worldguard IP: define verification strategy, develop scalable SystemVerilog/UVM testbenches, and deliver verification closure for processor and security features. Work within the design verification (DV) team and coordinate with architects and RTL engineers to ensure correctness and coverage.
Experience Level
Senior — 10+ years of design verification experience, preferably with CPU verification.
Responsibilities
Primary responsibilities include planning, implementation, and closure of verification activities for processor/security IP.
- Analyze architectural specifications and produce verification strategies and detailed test plans (test cases, checkers, coverage goals).
- Design and implement scalable, reusable constrained-random verification environments using SystemVerilog and UVM.
- Develop complex sequences and constrained-random stimulus to exercise corner cases; write C tests for processor-level verification where required.
- Perform deep-dive debug of RTL failures and testbench issues using waveform tools (e.g., Verdi, SimVision) and assist RTL teams with root-cause analysis.
- Define, track, and close functional and code coverage; implement covergroups and coverpoints to meet coverage goals.
- Own verification of security architecture features and drive delivery independently.
- Integrate and validate third-party VIPs and bus interfaces during system integration.
Requirements
Must-have skills and experience for the role, followed by preferred additions.
- Extensive hands-on experience with SystemVerilog and UVM (highly preferred); familiar with OVM or VMM.
- Strong RTL debugging skills and experience with waveform viewers and simulation flows.
- Proficiency in object-oriented programming and scripting (Python or Perl).
- Experience writing processor-level tests in C and performing processor verification.
- Knowledge of bus protocols such as AXI and AHB; experience with PCIe or similar is useful.
- Experience integrating and validating third-party VIPs (bus VIPs) in verification environments.
- Solid CPU microarchitecture understanding and experience with CPU verification (x86, ARM, or RISC-V).
Education Requirements
Bachelor's or Master's degree in Engineering (e.g., BE/BTech, ME/MTech) is specified in the posting.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
