Senior Staff Verification Engineer - High-Speed Interconnect

Job Title

Senior Staff Verification Engineer - High-Speed Interconnect

Role Summary

Lead end-to-end verification for high-speed interconnect IP (UCIe, PCIe, DDR) at Synopsys Hyderabad. Own test planning, UVM-based environment development, coverage closure, and silicon readiness for IP used in AI and compute platforms.

The role involves close collaboration with design, architecture, and silicon validation teams and mentoring junior verification engineers.

Experience Level

Senior - 7+ years of hands-on ASIC/SoC design verification experience (with at least 3 years on protocol-heavy IP).

Responsibilities

Drive verification from environment bring-up through sign-off and mentor others.

• Own verification of UCIe, PCIe, or DDR IP blocks: test planning, environment bring-up, coverage closure, and sign-off.
• Design and extend UVM testbenches (agents, sequencers, scoreboards, coverage models, protocol checkers).
• Write directed and constrained-random tests targeting protocol compliance, corner cases, and multi-layer interactions.
• Debug complex RTL and testbench failures using Verdi or equivalent tools; perform waveform, protocol trace, and transaction-level analysis.
• Translate protocol specifications into executable test plans, assertions (SVA), and functional coverage tied to silicon risk.
• Collaborate on bug triage, ECO impact analysis, and bring-up readiness with cross-functional teams.
• Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding; contribute to design and verification reviews.

Requirements

Must-have technical skills and experience required to perform the role.

• 7+ years of ASIC/SoC design verification experience, including at least 3 years on protocol-heavy IP.
• Deep working knowledge of one or more high-speed protocols: PCIe, UCIe, or DDR; able to read specs and build compliant testbenches.
• Strong UVM methodology experience: agents, constrained-random sequences, scoreboards, and functional coverage closure.
• Proficient in SystemVerilog including OOP, constrained-random stimulus, and SystemVerilog Assertions (SVA).
• Proven debug skills using Synopsys Verdi or equivalent (FSDB, protocol analyzers, transaction-level debug).
• Experience with industry simulators such as VCS, Xcelium, or Questa, and familiarity with regression/coverage tools (e.g., URG).
• Effective communicator able to explain verification risk to architects and design teams; experience mentoring junior engineers.

Nice-to-have: working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) and prior experience delivering verification that ran in silicon.

Education Requirements

B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or a related technical discipline (as stated). No alternative-equivalent-academic-language was provided in the source.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.